1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Renesas R-Car Timer Pulse Unit PWM Cont
8
9 maintainers:
10 - Laurent Pinchart <laurent.pinchart+renesas@
11
12 select:
13 properties:
14 compatible:
15 contains:
16 const: renesas,tpu
17 required:
18 - compatible
19 - '#pwm-cells'
20
21 properties:
22 compatible:
23 items:
24 - enum:
25 - renesas,tpu-r8a73a4 # R-Mobile A
26 - renesas,tpu-r8a7740 # R-Mobile A
27 - renesas,tpu-r8a7742 # RZ/G1H
28 - renesas,tpu-r8a7743 # RZ/G1M
29 - renesas,tpu-r8a7744 # RZ/G1N
30 - renesas,tpu-r8a7745 # RZ/G1E
31 - renesas,tpu-r8a7790 # R-Car H2
32 - renesas,tpu-r8a7791 # R-Car M2-W
33 - renesas,tpu-r8a7792 # R-Car V2H
34 - renesas,tpu-r8a7793 # R-Car M2-N
35 - renesas,tpu-r8a7794 # R-Car E2
36 - renesas,tpu-r8a7795 # R-Car H3
37 - renesas,tpu-r8a7796 # R-Car M3-W
38 - renesas,tpu-r8a77961 # R-Car M3-W
39 - renesas,tpu-r8a77965 # R-Car M3-N
40 - renesas,tpu-r8a77970 # R-Car V3M
41 - renesas,tpu-r8a77980 # R-Car V3H
42 - renesas,tpu-r8a779a0 # R-Car V3U
43 - renesas,tpu-r8a779g0 # R-Car V4H
44 - renesas,tpu-r8a779h0 # R-Car V4M
45 - const: renesas,tpu
46
47 reg:
48 # Base address and length of each memory r
49 # controller hardware module.
50 maxItems: 1
51
52 interrupts:
53 maxItems: 1
54
55 '#pwm-cells':
56 # should be 3. See pwm.yaml in this direct
57 # the cells format. The only third cell fl
58 # PWM_POLARITY_INVERTED.
59 const: 3
60
61 clocks:
62 maxItems: 1
63
64 power-domains:
65 maxItems: 1
66
67 resets:
68 maxItems: 1
69
70 required:
71 - compatible
72 - reg
73 - clocks
74 - power-domains
75
76 allOf:
77 - $ref: pwm.yaml#
78
79 - if:
80 not:
81 properties:
82 compatible:
83 contains:
84 enum:
85 - renesas,tpu-r8a73a4
86 - renesas,tpu-r8a7740
87 then:
88 required:
89 - resets
90
91 additionalProperties: false
92
93 examples:
94 - |
95 #include <dt-bindings/clock/r8a7740-clock.
96
97 tpu: pwm@e6600000 {
98 compatible = "renesas,tpu-r8a7740", "r
99 reg = <0xe6600000 0x148>;
100 clocks = <&mstp3_clks R8A7740_CLK_TPU0
101 power-domains = <&pd_a3sp>;
102 #pwm-cells = <3>;
103 };
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