1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ 4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SC7280 WPSS Peripheral Image L 7 title: Qualcomm SC7280 WPSS Peripheral Image Loader
8 8
9 maintainers: 9 maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org 10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 11
12 description: 12 description:
13 This document defines the binding for a comp 13 This document defines the binding for a component that loads and boots firmware
14 on the Qualcomm Technology Inc. WPSS. 14 on the Qualcomm Technology Inc. WPSS.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 enum: 18 enum:
19 - qcom,sc7280-wpss-pil 19 - qcom,sc7280-wpss-pil
20 20
21 reg: 21 reg:
22 maxItems: 1 22 maxItems: 1
23 description: 23 description:
24 The base address and size of the qdsp6ss 24 The base address and size of the qdsp6ss register
25 25
26 interrupts: 26 interrupts:
27 items: 27 items:
28 - description: Watchdog interrupt 28 - description: Watchdog interrupt
29 - description: Fatal interrupt 29 - description: Fatal interrupt
30 - description: Ready interrupt 30 - description: Ready interrupt
31 - description: Handover interrupt 31 - description: Handover interrupt
32 - description: Stop acknowledge interrup 32 - description: Stop acknowledge interrupt
33 - description: Shutdown acknowledge inte 33 - description: Shutdown acknowledge interrupt
34 34
35 interrupt-names: 35 interrupt-names:
36 items: 36 items:
37 - const: wdog 37 - const: wdog
38 - const: fatal 38 - const: fatal
39 - const: ready 39 - const: ready
40 - const: handover 40 - const: handover
41 - const: stop-ack 41 - const: stop-ack
42 - const: shutdown-ack 42 - const: shutdown-ack
43 43
44 clocks: 44 clocks:
45 items: 45 items:
46 - description: GCC WPSS AHB BDG Master c 46 - description: GCC WPSS AHB BDG Master clock
47 - description: GCC WPSS AHB clock 47 - description: GCC WPSS AHB clock
48 - description: GCC WPSS RSCP clock 48 - description: GCC WPSS RSCP clock
49 - description: XO clock 49 - description: XO clock
50 50
51 clock-names: 51 clock-names:
52 items: 52 items:
53 - const: ahb_bdg 53 - const: ahb_bdg
54 - const: ahb 54 - const: ahb
55 - const: rscp 55 - const: rscp
56 - const: xo 56 - const: xo
57 57
58 power-domains: 58 power-domains:
59 items: 59 items:
60 - description: CX power domain 60 - description: CX power domain
61 - description: MX power domain 61 - description: MX power domain
62 62
63 power-domain-names: 63 power-domain-names:
64 items: 64 items:
65 - const: cx 65 - const: cx
66 - const: mx 66 - const: mx
67 67
68 resets: 68 resets:
69 items: 69 items:
70 - description: AOSS restart 70 - description: AOSS restart
71 - description: PDC SYNC 71 - description: PDC SYNC
72 72
73 reset-names: 73 reset-names:
74 items: 74 items:
75 - const: restart 75 - const: restart
76 - const: pdc_sync 76 - const: pdc_sync
77 77
78 memory-region: 78 memory-region:
79 maxItems: 1 79 maxItems: 1
80 description: Reference to the reserved-mem 80 description: Reference to the reserved-memory for the Hexagon core
81 81
82 firmware-name: 82 firmware-name:
83 maxItems: 1 83 maxItems: 1
84 description: 84 description:
85 The name of the firmware which should be 85 The name of the firmware which should be loaded for this remote
86 processor. 86 processor.
87 87
88 qcom,halt-regs: 88 qcom,halt-regs:
89 $ref: /schemas/types.yaml#/definitions/pha 89 $ref: /schemas/types.yaml#/definitions/phandle-array
90 description: 90 description:
91 Phandle reference to a syscon representi 91 Phandle reference to a syscon representing TCSR followed by the
92 offset within syscon for q6 halt registe 92 offset within syscon for q6 halt register.
93 items: 93 items:
94 - items: 94 - items:
95 - description: phandle to TCSR sysco 95 - description: phandle to TCSR syscon region
96 - description: offset to the Q6 halt 96 - description: offset to the Q6 halt register
97 97
98 qcom,qmp: 98 qcom,qmp:
99 $ref: /schemas/types.yaml#/definitions/pha 99 $ref: /schemas/types.yaml#/definitions/phandle
100 description: Reference to the AOSS side-ch 100 description: Reference to the AOSS side-channel message RAM.
101 101
102 qcom,smem-states: 102 qcom,smem-states:
103 $ref: /schemas/types.yaml#/definitions/pha 103 $ref: /schemas/types.yaml#/definitions/phandle-array
104 description: States used by the AP to sign 104 description: States used by the AP to signal the Hexagon core
105 items: 105 items:
106 - description: Stop the modem 106 - description: Stop the modem
107 107
108 qcom,smem-state-names: 108 qcom,smem-state-names:
109 description: The names of the state bits u 109 description: The names of the state bits used for SMP2P output
110 const: stop 110 const: stop
111 111
112 glink-edge: 112 glink-edge:
113 $ref: qcom,glink-edge.yaml# 113 $ref: qcom,glink-edge.yaml#
114 unevaluatedProperties: false 114 unevaluatedProperties: false
115 description: 115 description:
116 Qualcomm G-Link subnode which represents 116 Qualcomm G-Link subnode which represents communication edge, channels
117 and devices related to the ADSP. 117 and devices related to the ADSP.
118 118
119 properties: 119 properties:
120 interrupts: 120 interrupts:
121 items: 121 items:
122 - description: IRQ from WPSS to GLIN 122 - description: IRQ from WPSS to GLINK
123 123
124 mboxes: 124 mboxes:
125 items: 125 items:
126 - description: Mailbox for communica 126 - description: Mailbox for communication between APPS and WPSS
127 127
128 label: 128 label:
129 items: 129 items:
130 - const: wpss 130 - const: wpss
131 131
132 apr: false 132 apr: false
133 fastrpc: false 133 fastrpc: false
134 134
135 required: 135 required:
136 - compatible 136 - compatible
137 - reg 137 - reg
138 - interrupts 138 - interrupts
139 - interrupt-names 139 - interrupt-names
140 - clocks 140 - clocks
141 - clock-names 141 - clock-names
142 - power-domains 142 - power-domains
143 - power-domain-names 143 - power-domain-names
144 - resets 144 - resets
145 - reset-names 145 - reset-names
146 - qcom,halt-regs 146 - qcom,halt-regs
147 - memory-region 147 - memory-region
148 - qcom,qmp 148 - qcom,qmp
149 - qcom,smem-states 149 - qcom,smem-states
150 - qcom,smem-state-names 150 - qcom,smem-state-names
151 - glink-edge 151 - glink-edge
152 152
153 additionalProperties: false 153 additionalProperties: false
154 154
155 examples: 155 examples:
156 - | 156 - |
157 #include <dt-bindings/interrupt-controller 157 #include <dt-bindings/interrupt-controller/arm-gic.h>
158 #include <dt-bindings/clock/qcom,gcc-sc728 158 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
159 #include <dt-bindings/clock/qcom,rpmh.h> 159 #include <dt-bindings/clock/qcom,rpmh.h>
160 #include <dt-bindings/power/qcom-rpmpd.h> 160 #include <dt-bindings/power/qcom-rpmpd.h>
161 #include <dt-bindings/reset/qcom,sdm845-ao 161 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
162 #include <dt-bindings/reset/qcom,sdm845-pd 162 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
163 #include <dt-bindings/mailbox/qcom-ipcc.h> 163 #include <dt-bindings/mailbox/qcom-ipcc.h>
164 remoteproc@8a00000 { 164 remoteproc@8a00000 {
165 compatible = "qcom,sc7280-wpss-pil"; 165 compatible = "qcom,sc7280-wpss-pil";
166 reg = <0x08a00000 0x10000>; 166 reg = <0x08a00000 0x10000>;
167 167
168 interrupts-extended = <&intc GIC_SPI 5 168 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
169 <&wpss_smp2p_in 169 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
170 <&wpss_smp2p_in 170 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
171 <&wpss_smp2p_in 171 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
172 <&wpss_smp2p_in 172 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
173 <&wpss_smp2p_in 173 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
174 interrupt-names = "wdog", "fatal", "re 174 interrupt-names = "wdog", "fatal", "ready", "handover",
175 "stop-ack", "shutdow 175 "stop-ack", "shutdown-ack";
176 176
177 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CL 177 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
178 <&gcc GCC_WPSS_AHB_CLK>, 178 <&gcc GCC_WPSS_AHB_CLK>,
179 <&gcc GCC_WPSS_RSCP_CLK>, 179 <&gcc GCC_WPSS_RSCP_CLK>,
180 <&rpmhcc RPMH_CXO_CLK>; 180 <&rpmhcc RPMH_CXO_CLK>;
181 clock-names = "ahb_bdg", "ahb", 181 clock-names = "ahb_bdg", "ahb",
182 "rscp", "xo"; 182 "rscp", "xo";
183 183
184 power-domains = <&rpmhpd SC7280_CX>, 184 power-domains = <&rpmhpd SC7280_CX>,
185 <&rpmhpd SC7280_MX>; 185 <&rpmhpd SC7280_MX>;
186 power-domain-names = "cx", "mx"; 186 power-domain-names = "cx", "mx";
187 187
188 memory-region = <&wpss_mem>; 188 memory-region = <&wpss_mem>;
189 189
190 qcom,qmp = <&aoss_qmp>; 190 qcom,qmp = <&aoss_qmp>;
191 191
192 qcom,smem-states = <&wpss_smp2p_out 0> 192 qcom,smem-states = <&wpss_smp2p_out 0>;
193 qcom,smem-state-names = "stop"; 193 qcom,smem-state-names = "stop";
194 194
195 resets = <&aoss_reset AOSS_CC_WCSS_RES 195 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
196 <&pdc_reset PDC_WPSS_SYNC_RES 196 <&pdc_reset PDC_WPSS_SYNC_RESET>;
197 reset-names = "restart", "pdc_sync"; 197 reset-names = "restart", "pdc_sync";
198 198
199 qcom,halt-regs = <&tcsr_mutex 0x37000> 199 qcom,halt-regs = <&tcsr_mutex 0x37000>;
200 200
201 glink-edge { 201 glink-edge {
202 interrupts-extended = <&ipcc IPCC_ 202 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
203 IPCC_ 203 IPCC_MPROC_SIGNAL_GLINK_QMP
204 IRQ_T 204 IRQ_TYPE_EDGE_RISING>;
205 mboxes = <&ipcc IPCC_CLIENT_WPSS 205 mboxes = <&ipcc IPCC_CLIENT_WPSS
206 IPCC_MPROC_SIGNAL_ 206 IPCC_MPROC_SIGNAL_GLINK_QMP>;
207 207
208 label = "wpss"; 208 label = "wpss";
209 qcom,remote-pid = <13>; 209 qcom,remote-pid = <13>;
210 }; 210 };
211 }; 211 };
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