1 # SPDX-License-Identifier: (GPL-2.0-only OR BS !! 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: TI K3 R5F processor subsystems 7 title: TI K3 R5F processor subsystems
8 8
9 maintainers: 9 maintainers:
10 - Suman Anna <s-anna@ti.com> 10 - Suman Anna <s-anna@ti.com>
11 11
12 description: | 12 description: |
13 The TI K3 family of SoCs usually have one or 13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The d 14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
15 either in a LockStep mode providing safety/f 15 either in a LockStep mode providing safety/fault tolerance features or in a
16 Split mode providing two individual compute 16 Split mode providing two individual compute cores for doubling the compute
17 capacity on most SoCs. These are used togeth 17 capacity on most SoCs. These are used together with other processors present
18 on the SoC to achieve various system level g 18 on the SoC to achieve various system level goals.
19 19
20 AM64x SoCs do not support LockStep mode, but 20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 i 21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
22 Core1's TCMs as well. 22 Core1's TCMs as well.
23 23
24 AM62 SoC family support a single R5F core on <<
25 firmware and can also be used as a remote pr <<
26 <<
27 Each Dual-Core R5F sub-system is represented 24 Each Dual-Core R5F sub-system is represented as a single DTS node
28 representing the cluster, with a pair of chi 25 representing the cluster, with a pair of child DT nodes representing
29 the individual R5F cores. Each node has a nu 26 the individual R5F cores. Each node has a number of required or optional
30 properties that enable the OS running on the 27 properties that enable the OS running on the host processor to perform
31 the device management of the remote processo 28 the device management of the remote processor and to communicate with the
32 remote processor. 29 remote processor.
33 30
34 properties: 31 properties:
35 $nodename: 32 $nodename:
36 pattern: "^r5fss(@.*)?" 33 pattern: "^r5fss(@.*)?"
37 34
38 compatible: 35 compatible:
39 enum: 36 enum:
40 - ti,am62-r5fss <<
41 - ti,am64-r5fss <<
42 - ti,am654-r5fss 37 - ti,am654-r5fss
43 - ti,j7200-r5fss <<
44 - ti,j721e-r5fss 38 - ti,j721e-r5fss
45 - ti,j721s2-r5fss !! 39 - ti,j7200-r5fss
>> 40 - ti,am64-r5fss
46 41
47 power-domains: 42 power-domains:
48 description: | 43 description: |
49 Should contain a phandle to a PM domain 44 Should contain a phandle to a PM domain provider node and an args
50 specifier containing the R5FSS device id 45 specifier containing the R5FSS device id value.
51 maxItems: 1 46 maxItems: 1
52 47
53 "#address-cells": 48 "#address-cells":
54 const: 1 49 const: 1
55 50
56 "#size-cells": 51 "#size-cells":
57 const: 1 52 const: 1
58 53
59 ranges: 54 ranges:
60 description: | 55 description: |
61 Standard ranges definition providing add 56 Standard ranges definition providing address translations for
62 local R5F TCM address spaces to bus addr 57 local R5F TCM address spaces to bus addresses.
63 58
64 # Optional properties: 59 # Optional properties:
65 # -------------------- 60 # --------------------
66 61
67 ti,cluster-mode: 62 ti,cluster-mode:
68 $ref: /schemas/types.yaml#/definitions/uin 63 $ref: /schemas/types.yaml#/definitions/uint32
69 description: | 64 description: |
70 Configuration Mode for the Dual R5F core 65 Configuration Mode for the Dual R5F cores within the R5F cluster.
71 For most SoCs (AM65x, J721E, J7200, J721 !! 66 Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
72 It should be either a value of 1 (LockSt !! 67 most SoCs (AM65x, J721E, J7200), default is LockStep mode if omitted;
73 most SoCs (AM65x, J721E, J7200, J721s2), !! 68 and should be either a value of 0 (Split mode) or 2 (Single-CPU mode)
74 omitted. !! 69 on AM64x SoCs, default is Split mode if omitted.
75 For AM64x SoCs, <<
76 It should be either a value of 0 (Split <<
77 default is Split mode if omitted. <<
78 For AM62x SoCs, <<
79 It should be set as 3 (Single-Core mode) <<
80 omitted. <<
81 <<
82 70
83 # R5F Processor Child Nodes: 71 # R5F Processor Child Nodes:
84 # ========================== 72 # ==========================
85 73
86 patternProperties: 74 patternProperties:
87 "^r5f@[a-f0-9]+$": 75 "^r5f@[a-f0-9]+$":
88 type: object 76 type: object
89 description: | 77 description: |
90 The R5F Sub-System device node should de 78 The R5F Sub-System device node should define two R5F child nodes, each
91 node representing a TI instantiation of 79 node representing a TI instantiation of the Arm Cortex R5F core. There
92 are some specific integration difference 80 are some specific integration differences for the IP like the usage of
93 a Region Address Translator (RAT) for tr 81 a Region Address Translator (RAT) for translating the larger SoC bus
94 addresses into a 32-bit address space fo !! 82 addresses into a 32-bit address space for the processor.
95 the R5F Sub-System device node should on <<
96 as it has only one core available. <<
97 83
98 Each R5F core has an associated 64 KB of 84 Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
99 internal memories split between two bank 85 internal memories split between two banks - TCMA and TCMB (further
100 interleaved into two banks TCMB0 and TCM 86 interleaved into two banks TCMB0 and TCMB1). These memories (also called
101 ATCM and BTCM) provide read/write perfor 87 ATCM and BTCM) provide read/write performance on par with the core's L1
102 caches. Each of the TCMs can be enabled 88 caches. Each of the TCMs can be enabled or disabled independently and
103 either of them can be configured to appe 89 either of them can be configured to appear at that R5F's address 0x0.
104 90
105 The cores do not use an MMU, but has a R !! 91 The cores do not use an MMU, but has a Region Address Translater
106 (RAT) module that is accessible only fro 92 (RAT) module that is accessible only from the R5Fs for providing
107 translations between 32-bit CPU addresse 93 translations between 32-bit CPU addresses into larger system bus
108 addresses. Cache and memory access setti 94 addresses. Cache and memory access settings are provided through a
109 Memory Protection Unit (MPU), programmab 95 Memory Protection Unit (MPU), programmable only from the R5Fs.
110 96
111 $ref: /schemas/arm/keystone/ti,k3-sci-comm !! 97 allOf:
>> 98 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
112 99
113 properties: 100 properties:
114 compatible: 101 compatible:
115 enum: 102 enum:
116 - ti,am62-r5f <<
117 - ti,am64-r5f <<
118 - ti,am654-r5f 103 - ti,am654-r5f
119 - ti,j7200-r5f <<
120 - ti,j721e-r5f 104 - ti,j721e-r5f
121 - ti,j721s2-r5f !! 105 - ti,j7200-r5f
>> 106 - ti,am64-r5f
122 107
123 reg: 108 reg:
124 items: 109 items:
125 - description: Address and Size of t 110 - description: Address and Size of the ATCM internal memory region
126 - description: Address and Size of t 111 - description: Address and Size of the BTCM internal memory region
127 112
128 reg-names: 113 reg-names:
129 items: 114 items:
130 - const: atcm 115 - const: atcm
131 - const: btcm 116 - const: btcm
132 117
133 resets: 118 resets:
134 description: | 119 description: |
135 Should contain the phandle to the re 120 Should contain the phandle to the reset controller node managing the
136 local resets for this device, and a 121 local resets for this device, and a reset specifier.
137 maxItems: 1 122 maxItems: 1
138 123
139 firmware-name: 124 firmware-name:
140 description: | 125 description: |
141 Should contain the name of the defau 126 Should contain the name of the default firmware image
142 file located on the firmware search 127 file located on the firmware search path
143 128
144 # The following properties are mandatory for R 129 # The following properties are mandatory for R5F Core0 in both LockStep and Split
145 # modes, and are mandatory for R5F Core1 _only 130 # modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
146 # R5F Core1 in LockStep mode: 131 # R5F Core1 in LockStep mode:
147 132
148 mboxes: 133 mboxes:
149 description: | 134 description: |
150 OMAP Mailbox specifier denoting the 135 OMAP Mailbox specifier denoting the sub-mailbox, to be used for
151 communication with the remote proces 136 communication with the remote processor. This property should match
152 with the sub-mailbox node used in th 137 with the sub-mailbox node used in the firmware image.
153 maxItems: 1 138 maxItems: 1
154 139
155 memory-region: 140 memory-region:
156 description: | 141 description: |
157 phandle to the reserved memory nodes 142 phandle to the reserved memory nodes to be associated with the
158 remoteproc device. There should be a 143 remoteproc device. There should be at least two reserved memory nodes
159 defined. The reserved memory nodes s 144 defined. The reserved memory nodes should be carveout nodes, and
160 should be defined with a "no-map" pr 145 should be defined with a "no-map" property as per the bindings in
161 Documentation/devicetree/bindings/re 146 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
162 minItems: 2 147 minItems: 2
163 maxItems: 8 148 maxItems: 8
164 items: 149 items:
165 - description: region used for dynam 150 - description: region used for dynamic DMA allocations like vrings and
166 vring buffers 151 vring buffers
167 - description: region reserved for f 152 - description: region reserved for firmware image sections
168 additionalItems: true 153 additionalItems: true
169 154
170 155
171 # Optional properties: 156 # Optional properties:
172 # -------------------- 157 # --------------------
173 # The following properties are optional proper 158 # The following properties are optional properties for each of the R5F cores:
174 159
175 ti,atcm-enable: 160 ti,atcm-enable:
176 $ref: /schemas/types.yaml#/definitions 161 $ref: /schemas/types.yaml#/definitions/uint32
177 enum: [0, 1] 162 enum: [0, 1]
178 description: | 163 description: |
179 R5F core configuration mode dictatin 164 R5F core configuration mode dictating if ATCM should be enabled. The
180 R5F address of ATCM is dictated by t 165 R5F address of ATCM is dictated by ti,loczrama property. Should be
181 either a value of 1 (enabled) or 0 ( 166 either a value of 1 (enabled) or 0 (disabled), default is disabled
182 if omitted. Recommended to enable it 167 if omitted. Recommended to enable it for maximizing TCMs.
183 168
184 ti,btcm-enable: 169 ti,btcm-enable:
185 $ref: /schemas/types.yaml#/definitions 170 $ref: /schemas/types.yaml#/definitions/uint32
186 enum: [0, 1] 171 enum: [0, 1]
187 description: | 172 description: |
188 R5F core configuration mode dictatin 173 R5F core configuration mode dictating if BTCM should be enabled. The
189 R5F address of BTCM is dictated by t 174 R5F address of BTCM is dictated by ti,loczrama property. Should be
190 either a value of 1 (enabled) or 0 ( 175 either a value of 1 (enabled) or 0 (disabled), default is enabled if
191 omitted. 176 omitted.
192 177
193 ti,loczrama: 178 ti,loczrama:
194 $ref: /schemas/types.yaml#/definitions 179 $ref: /schemas/types.yaml#/definitions/uint32
195 enum: [0, 1] 180 enum: [0, 1]
196 description: | 181 description: |
197 R5F core configuration mode dictatin 182 R5F core configuration mode dictating which TCM should appear at
198 address 0 (from core's view). Should 183 address 0 (from core's view). Should be either a value of 1 (ATCM
199 at 0x0) or 0 (BTCM at 0x0), default 184 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
200 185
201 sram: 186 sram:
202 $ref: /schemas/types.yaml#/definitions 187 $ref: /schemas/types.yaml#/definitions/phandle-array
203 minItems: 1 188 minItems: 1
204 maxItems: 4 189 maxItems: 4
205 items: <<
206 maxItems: 1 <<
207 description: | 190 description: |
208 phandles to one or more reserved on- 191 phandles to one or more reserved on-chip SRAM regions. The regions
209 should be defined as child nodes of 192 should be defined as child nodes of the respective SRAM node, and
210 should be defined as per the generic 193 should be defined as per the generic bindings in,
211 Documentation/devicetree/bindings/sr 194 Documentation/devicetree/bindings/sram/sram.yaml
212 195
213 required: 196 required:
214 - compatible 197 - compatible
215 - reg 198 - reg
216 - reg-names 199 - reg-names
217 - ti,sci 200 - ti,sci
218 - ti,sci-dev-id 201 - ti,sci-dev-id
219 - ti,sci-proc-ids 202 - ti,sci-proc-ids
220 - resets 203 - resets
221 - firmware-name 204 - firmware-name
222 205
223 unevaluatedProperties: false 206 unevaluatedProperties: false
224 207
225 allOf: !! 208 if:
226 - if: !! 209 properties:
227 properties: !! 210 compatible:
228 compatible: !! 211 enum:
229 enum: !! 212 - ti,am64-r5fss
230 - ti,am64-r5fss !! 213 then:
231 then: !! 214 properties:
232 properties: !! 215 ti,cluster-mode:
233 ti,cluster-mode: !! 216 enum: [0, 2]
234 enum: [0, 2] !! 217 else:
235 !! 218 properties:
236 - if: !! 219 ti,cluster-mode:
237 properties: !! 220 enum: [0, 1]
238 compatible: <<
239 enum: <<
240 - ti,am654-r5fss <<
241 - ti,j7200-r5fss <<
242 - ti,j721e-r5fss <<
243 - ti,j721s2-r5fss <<
244 then: <<
245 properties: <<
246 ti,cluster-mode: <<
247 enum: [0, 1] <<
248 <<
249 - if: <<
250 properties: <<
251 compatible: <<
252 enum: <<
253 - ti,am62-r5fss <<
254 then: <<
255 properties: <<
256 ti,cluster-mode: <<
257 enum: [3] <<
258 221
259 required: 222 required:
260 - compatible 223 - compatible
261 - power-domains 224 - power-domains
262 - "#address-cells" 225 - "#address-cells"
263 - "#size-cells" 226 - "#size-cells"
264 - ranges 227 - ranges
265 228
266 additionalProperties: false 229 additionalProperties: false
267 230
268 examples: 231 examples:
269 - | 232 - |
270 soc { 233 soc {
271 #address-cells = <2>; 234 #address-cells = <2>;
272 #size-cells = <2>; 235 #size-cells = <2>;
273 <<
274 mailbox0: mailbox-0 { <<
275 #mbox-cells = <1>; <<
276 }; <<
277 <<
278 mailbox1: mailbox-1 { <<
279 #mbox-cells = <1>; <<
280 }; <<
281 236
282 bus@100000 { 237 bus@100000 {
283 compatible = "simple-bus"; 238 compatible = "simple-bus";
284 #address-cells = <2>; 239 #address-cells = <2>;
285 #size-cells = <2>; 240 #size-cells = <2>;
286 ranges = <0x00 0x00100000 0x00 0x0 241 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
287 <0x00 0x41000000 0x00 0x4 242 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
288 <0x00 0x41400000 0x00 0x4 243 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
289 <0x00 0x41c00000 0x00 0x4 244 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
290 245
291 bus@28380000 { 246 bus@28380000 {
292 compatible = "simple-bus"; 247 compatible = "simple-bus";
293 #address-cells = <2>; 248 #address-cells = <2>;
294 #size-cells = <2>; 249 #size-cells = <2>;
295 ranges = <0x00 0x28380000 0x00 250 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
296 <0x00 0x41000000 0x00 251 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
297 <0x00 0x41400000 0x00 252 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
298 <0x00 0x41c00000 0x00 253 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
299 254
300 /* AM65x MCU R5FSS node */ 255 /* AM65x MCU R5FSS node */
301 mcu_r5fss0: r5fss@41000000 { 256 mcu_r5fss0: r5fss@41000000 {
302 compatible = "ti,am654-r5f 257 compatible = "ti,am654-r5fss";
303 power-domains = <&k3_pds 1 258 power-domains = <&k3_pds 129>;
304 ti,cluster-mode = <1>; 259 ti,cluster-mode = <1>;
305 #address-cells = <1>; 260 #address-cells = <1>;
306 #size-cells = <1>; 261 #size-cells = <1>;
307 ranges = <0x41000000 0x00 262 ranges = <0x41000000 0x00 0x41000000 0x20000>,
308 <0x41400000 0x00 263 <0x41400000 0x00 0x41400000 0x20000>;
309 264
310 mcu_r5f0: r5f@41000000 { 265 mcu_r5f0: r5f@41000000 {
311 compatible = "ti,am654 266 compatible = "ti,am654-r5f";
312 reg = <0x41000000 0x00 267 reg = <0x41000000 0x00008000>,
313 <0x41010000 0x00 268 <0x41010000 0x00008000>;
314 reg-names = "atcm", "b 269 reg-names = "atcm", "btcm";
315 ti,sci = <&dmsc>; 270 ti,sci = <&dmsc>;
316 ti,sci-dev-id = <159>; 271 ti,sci-dev-id = <159>;
317 ti,sci-proc-ids = <0x0 272 ti,sci-proc-ids = <0x01 0xFF>;
318 resets = <&k3_reset 15 273 resets = <&k3_reset 159 1>;
319 firmware-name = "am65x 274 firmware-name = "am65x-mcu-r5f0_0-fw";
320 ti,atcm-enable = <1>; 275 ti,atcm-enable = <1>;
321 ti,btcm-enable = <1>; 276 ti,btcm-enable = <1>;
322 ti,loczrama = <1>; 277 ti,loczrama = <1>;
323 mboxes = <&mailbox0 &m 278 mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
324 memory-region = <&mcu_ 279 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
325 <&mcu_ 280 <&mcu_r5fss0_core0_memory_region>;
326 sram = <&mcu_r5fss0_co 281 sram = <&mcu_r5fss0_core0_sram>;
327 }; 282 };
328 283
329 mcu_r5f1: r5f@41400000 { 284 mcu_r5f1: r5f@41400000 {
330 compatible = "ti,am654 285 compatible = "ti,am654-r5f";
331 reg = <0x41400000 0x00 286 reg = <0x41400000 0x00008000>,
332 <0x41410000 0x00 287 <0x41410000 0x00008000>;
333 reg-names = "atcm", "b 288 reg-names = "atcm", "btcm";
334 ti,sci = <&dmsc>; 289 ti,sci = <&dmsc>;
335 ti,sci-dev-id = <245>; 290 ti,sci-dev-id = <245>;
336 ti,sci-proc-ids = <0x0 291 ti,sci-proc-ids = <0x02 0xFF>;
337 resets = <&k3_reset 24 292 resets = <&k3_reset 245 1>;
338 firmware-name = "am65x 293 firmware-name = "am65x-mcu-r5f0_1-fw";
339 ti,atcm-enable = <1>; 294 ti,atcm-enable = <1>;
340 ti,btcm-enable = <1>; 295 ti,btcm-enable = <1>;
341 ti,loczrama = <1>; 296 ti,loczrama = <1>;
342 mboxes = <&mailbox1 &m 297 mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;
343 }; 298 };
344 }; 299 };
345 }; 300 };
346 }; 301 };
347 }; 302 };
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