1 # SPDX-License-Identifier: (GPL-2.0-only OR BS !! 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ 4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: OMAP4+ Remoteproc Devices 7 title: OMAP4+ Remoteproc Devices
8 8
9 maintainers: 9 maintainers:
10 - Suman Anna <s-anna@ti.com> 10 - Suman Anna <s-anna@ti.com>
11 11
12 description: 12 description:
13 The OMAP family of SoCs usually have one or 13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the process 14 that are used to offload some of the processor-intensive tasks, or to manage
15 other hardware accelerators, for achieving v 15 other hardware accelerators, for achieving various system level goals.
16 16
17 The processor cores in the sub-system are us 17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal 18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
19 caches, an Interrupt Controller, a Cache Con 19 caches, an Interrupt Controller, a Cache Controller etc.
20 20
21 The OMAP SoCs usually have a DSP processor s 21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
22 sub-system. The DSP processor sub-system can 22 sub-system. The DSP processor sub-system can contain any of the TI's C64x,
23 C66x or C67x family of DSP cores as the main 23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
24 sub-system usually contains either a Dual-Co 24 sub-system usually contains either a Dual-Core Cortex-M3 or Dual-Core
25 Cortex-M4 processors. 25 Cortex-M4 processors.
26 26
27 Each remote processor sub-system is represen 27 Each remote processor sub-system is represented as a single DT node. Each node
28 has a number of required or optional propert 28 has a number of required or optional properties that enable the OS running on
29 the host processor (MPU) to perform the devi 29 the host processor (MPU) to perform the device management of the remote
30 processor and to communicate with the remote 30 processor and to communicate with the remote processor. The various properties
31 can be classified as constant or variable. T 31 can be classified as constant or variable. The constant properties are
32 dictated by the SoC and does not change from 32 dictated by the SoC and does not change from one board to another having the
33 same SoC. Examples of constant properties in 33 same SoC. Examples of constant properties include 'iommus', 'reg'. The
34 variable properties are dictated by the syst 34 variable properties are dictated by the system integration aspects such as
35 memory on the board, or configuration used w 35 memory on the board, or configuration used within the corresponding firmware
36 image. Examples of variable properties inclu 36 image. Examples of variable properties include 'mboxes', 'memory-region',
37 'timers', 'watchdog-timers' etc. 37 'timers', 'watchdog-timers' etc.
38 38
39 properties: 39 properties:
40 compatible: 40 compatible:
41 enum: 41 enum:
42 - ti,omap4-dsp 42 - ti,omap4-dsp
43 - ti,omap5-dsp 43 - ti,omap5-dsp
44 - ti,dra7-dsp 44 - ti,dra7-dsp
45 - ti,omap4-ipu 45 - ti,omap4-ipu
46 - ti,omap5-ipu 46 - ti,omap5-ipu
47 - ti,dra7-ipu 47 - ti,dra7-ipu
48 48
49 iommus: 49 iommus:
50 minItems: 1 50 minItems: 1
51 maxItems: 2 51 maxItems: 2
52 description: | 52 description: |
53 phandles to OMAP IOMMU nodes, that need 53 phandles to OMAP IOMMU nodes, that need to be programmed
54 for this remote processor to access any 54 for this remote processor to access any external RAM memory or
55 other peripheral device address spaces. 55 other peripheral device address spaces. This property usually
56 has only a single phandle. Multiple phan 56 has only a single phandle. Multiple phandles are used only in
57 cases where the sub-system has different 57 cases where the sub-system has different ports for different
58 sub-modules within the processor sub-sys 58 sub-modules within the processor sub-system (eg: DRA7 DSPs),
59 and need the same programming in both th 59 and need the same programming in both the MMUs.
60 60
61 mboxes: 61 mboxes:
62 minItems: 1 62 minItems: 1
63 maxItems: 2 63 maxItems: 2
64 description: | 64 description: |
65 OMAP Mailbox specifier denoting the sub- 65 OMAP Mailbox specifier denoting the sub-mailbox, to be used for
66 communication with the remote processor. 66 communication with the remote processor. The specifier format is
67 as per the bindings, 67 as per the bindings,
68 Documentation/devicetree/bindings/mailbo !! 68 Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
69 This property should match with the sub- 69 This property should match with the sub-mailbox node used in
70 the firmware image. 70 the firmware image.
71 71
72 clocks: 72 clocks:
73 maxItems: 1 <<
74 description: | 73 description: |
75 Main functional clock for the remote pro 74 Main functional clock for the remote processor
76 75
77 resets: 76 resets:
78 minItems: 1 <<
79 maxItems: 2 <<
80 description: | 77 description: |
81 Reset handles for the remote processor 78 Reset handles for the remote processor
82 79
83 firmware-name: 80 firmware-name:
84 description: | 81 description: |
85 Default name of the firmware to load to 82 Default name of the firmware to load to the remote processor.
86 83
87 # Optional properties: 84 # Optional properties:
88 # -------------------- 85 # --------------------
89 # Some of these properties are mandatory on so 86 # Some of these properties are mandatory on some SoCs, and some are optional
90 # depending on the configuration of the firmwa 87 # depending on the configuration of the firmware image to be executed on the
91 # remote processor. The conditions are mention 88 # remote processor. The conditions are mentioned for each property.
92 # 89 #
93 # The following are the optional properties: 90 # The following are the optional properties:
94 91
95 memory-region: 92 memory-region:
96 maxItems: 1 !! 93 $ref: /schemas/types.yaml#/definitions/phandle
97 description: | 94 description: |
98 phandle to the reserved memory node to b 95 phandle to the reserved memory node to be associated
99 with the remoteproc device. The reserved 96 with the remoteproc device. The reserved memory node
100 can be a CMA memory node, and should be 97 can be a CMA memory node, and should be defined as
101 per the bindings, 98 per the bindings,
102 Documentation/devicetree/bindings/reserv 99 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
103 100
104 reg: 101 reg:
105 description: | 102 description: |
106 Address space for any remoteproc memorie 103 Address space for any remoteproc memories present on
107 the SoC. Should contain an entry for eac 104 the SoC. Should contain an entry for each value in
108 'reg-names'. These are mandatory for all 105 'reg-names'. These are mandatory for all DSP and IPU
109 processors that have them (OMAP4/OMAP5 D 106 processors that have them (OMAP4/OMAP5 DSPs do not have
110 any RAMs) 107 any RAMs)
111 108
112 reg-names: 109 reg-names:
113 description: | 110 description: |
114 Required names for each of the address s 111 Required names for each of the address spaces defined in
115 the 'reg' property. Expects the names fr 112 the 'reg' property. Expects the names from the following
116 list, in the specified order, each repre 113 list, in the specified order, each representing the corresponding
117 internal RAM memory region. 114 internal RAM memory region.
118 minItems: 1 115 minItems: 1
>> 116 maxItems: 3
119 items: 117 items:
120 - const: l2ram 118 - const: l2ram
121 - const: l1pram 119 - const: l1pram
122 - const: l1dram 120 - const: l1dram
123 121
124 ti,bootreg: 122 ti,bootreg:
125 $ref: /schemas/types.yaml#/definitions/pha 123 $ref: /schemas/types.yaml#/definitions/phandle-array
126 items: !! 124 description: |
127 - items: !! 125 Should be a triple of the phandle to the System Control
128 - description: phandle to the System !! 126 Configuration region that contains the boot address
129 - description: register offset of th !! 127 register, the register offset of the boot address
130 - description: the bit shift within !! 128 register within the System Control module, and the bit
131 description: !! 129 shift within the register. This property is required for
132 This property is required for all the DS !! 130 all the DSP instances on OMAP4, OMAP5 and DRA7xx SoCs.
133 and DRA7xx SoCs. <<
134 131
135 ti,autosuspend-delay-ms: 132 ti,autosuspend-delay-ms:
136 description: | 133 description: |
137 Custom autosuspend delay for the remotep 134 Custom autosuspend delay for the remoteproc in milliseconds.
138 Recommended values is preferable to be i 135 Recommended values is preferable to be in the order of couple
139 of seconds. A negative value can also be 136 of seconds. A negative value can also be used to disable the
140 autosuspend behavior. 137 autosuspend behavior.
141 138
142 ti,timers: 139 ti,timers:
143 $ref: /schemas/types.yaml#/definitions/pha 140 $ref: /schemas/types.yaml#/definitions/phandle-array
144 items: <<
145 maxItems: 1 <<
146 description: | 141 description: |
147 One or more phandles to OMAP DMTimer nod 142 One or more phandles to OMAP DMTimer nodes, that serve
148 as System/Tick timers for the OS running 143 as System/Tick timers for the OS running on the remote
149 processors. This will usually be a singl 144 processors. This will usually be a single timer if the
150 processor sub-system is running in SMP m 145 processor sub-system is running in SMP mode, or one per
151 core in the processor sub-system. This c 146 core in the processor sub-system. This can also be used
152 to reserve specific timers to be dedicat 147 to reserve specific timers to be dedicated to the
153 remote processors. 148 remote processors.
154 149
155 This property is mandatory on remote pro 150 This property is mandatory on remote processors requiring
156 external tick wakeup, and to support Pow 151 external tick wakeup, and to support Power Management
157 features. The timers to be used should m 152 features. The timers to be used should match with the
158 timers used in the firmware image. 153 timers used in the firmware image.
159 154
160 ti,watchdog-timers: 155 ti,watchdog-timers:
161 $ref: /schemas/types.yaml#/definitions/pha 156 $ref: /schemas/types.yaml#/definitions/phandle-array
162 items: <<
163 maxItems: 1 <<
164 description: | 157 description: |
165 One or more phandles to OMAP DMTimer nod 158 One or more phandles to OMAP DMTimer nodes, used to
166 serve as Watchdog timers for the process 159 serve as Watchdog timers for the processor cores. This
167 will usually be one per executing proces 160 will usually be one per executing processor core, even
168 if the processor sub-system is running a 161 if the processor sub-system is running a SMP OS.
169 162
170 The timers to be used should match with 163 The timers to be used should match with the watchdog
171 timers used in the firmware image. 164 timers used in the firmware image.
172 165
173 if: 166 if:
174 properties: 167 properties:
175 compatible: 168 compatible:
176 enum: 169 enum:
177 - ti,dra7-dsp 170 - ti,dra7-dsp
178 then: 171 then:
179 properties: 172 properties:
180 reg: 173 reg:
181 minItems: 3 174 minItems: 3
182 maxItems: 3 175 maxItems: 3
183 required: 176 required:
184 - reg 177 - reg
185 - reg-names 178 - reg-names
186 - ti,bootreg 179 - ti,bootreg
187 180
188 else: 181 else:
189 if: 182 if:
190 properties: 183 properties:
191 compatible: 184 compatible:
192 enum: 185 enum:
193 - ti,omap4-ipu 186 - ti,omap4-ipu
194 - ti,omap5-ipu 187 - ti,omap5-ipu
195 - ti,dra7-ipu 188 - ti,dra7-ipu
196 then: 189 then:
197 properties: 190 properties:
198 reg: 191 reg:
199 minItems: 1 192 minItems: 1
200 maxItems: 1 193 maxItems: 1
201 ti,bootreg: false 194 ti,bootreg: false
202 required: 195 required:
203 - reg 196 - reg
204 - reg-names 197 - reg-names
205 198
206 else: 199 else:
207 properties: 200 properties:
208 reg: false 201 reg: false
209 required: 202 required:
210 - ti,bootreg 203 - ti,bootreg
211 204
212 required: 205 required:
213 - compatible 206 - compatible
214 - iommus 207 - iommus
215 - mboxes 208 - mboxes
216 - clocks 209 - clocks
217 - resets 210 - resets
218 - firmware-name 211 - firmware-name
219 212
220 additionalProperties: false 213 additionalProperties: false
221 214
222 examples: 215 examples:
223 - | 216 - |
224 217
225 //Example 1: OMAP4 DSP 218 //Example 1: OMAP4 DSP
226 219
227 /* DSP Reserved Memory node */ 220 /* DSP Reserved Memory node */
228 #include <dt-bindings/clock/omap4.h> 221 #include <dt-bindings/clock/omap4.h>
229 reserved-memory { 222 reserved-memory {
230 #address-cells = <1>; 223 #address-cells = <1>;
231 #size-cells = <1>; 224 #size-cells = <1>;
232 225
233 dsp_memory_region: dsp-memory@98000000 226 dsp_memory_region: dsp-memory@98000000 {
234 compatible = "shared-dma-pool"; 227 compatible = "shared-dma-pool";
235 reg = <0x98000000 0x800000>; 228 reg = <0x98000000 0x800000>;
236 reusable; 229 reusable;
237 }; 230 };
238 }; 231 };
239 232
240 /* DSP node */ 233 /* DSP node */
241 ocp { 234 ocp {
242 dsp: dsp { 235 dsp: dsp {
243 compatible = "ti,omap4-dsp"; 236 compatible = "ti,omap4-dsp";
244 ti,bootreg = <&scm_conf 0x304 0>; 237 ti,bootreg = <&scm_conf 0x304 0>;
245 iommus = <&mmu_dsp>; 238 iommus = <&mmu_dsp>;
246 mboxes = <&mailbox &mbox_dsp>; 239 mboxes = <&mailbox &mbox_dsp>;
247 memory-region = <&dsp_memory_regio 240 memory-region = <&dsp_memory_region>;
248 ti,timers = <&timer5>; 241 ti,timers = <&timer5>;
249 ti,watchdog-timers = <&timer6>; 242 ti,watchdog-timers = <&timer6>;
250 clocks = <&tesla_clkctrl OMAP4_DSP 243 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
251 resets = <&prm_tesla 0>, <&prm_tes 244 resets = <&prm_tesla 0>, <&prm_tesla 1>;
252 firmware-name = "omap4-dsp-fw.xe64 245 firmware-name = "omap4-dsp-fw.xe64T";
253 }; 246 };
254 }; 247 };
255 248
256 - |+ 249 - |+
257 250
258 //Example 2: OMAP5 IPU 251 //Example 2: OMAP5 IPU
259 252
260 /* IPU Reserved Memory node */ 253 /* IPU Reserved Memory node */
261 #include <dt-bindings/clock/omap5.h> 254 #include <dt-bindings/clock/omap5.h>
262 reserved-memory { 255 reserved-memory {
263 #address-cells = <2>; 256 #address-cells = <2>;
264 #size-cells = <2>; 257 #size-cells = <2>;
265 258
266 ipu_memory_region: ipu-memory@95800000 259 ipu_memory_region: ipu-memory@95800000 {
267 compatible = "shared-dma-pool"; 260 compatible = "shared-dma-pool";
268 reg = <0 0x95800000 0 0x3800000>; 261 reg = <0 0x95800000 0 0x3800000>;
269 reusable; 262 reusable;
270 }; 263 };
271 }; 264 };
272 265
273 /* IPU node */ 266 /* IPU node */
274 ocp { 267 ocp {
275 #address-cells = <1>; 268 #address-cells = <1>;
276 #size-cells = <1>; 269 #size-cells = <1>;
277 270
278 ipu: ipu@55020000 { 271 ipu: ipu@55020000 {
279 compatible = "ti,omap5-ipu"; 272 compatible = "ti,omap5-ipu";
280 reg = <0x55020000 0x10000>; 273 reg = <0x55020000 0x10000>;
281 reg-names = "l2ram"; 274 reg-names = "l2ram";
282 iommus = <&mmu_ipu>; 275 iommus = <&mmu_ipu>;
283 mboxes = <&mailbox &mbox_ipu>; 276 mboxes = <&mailbox &mbox_ipu>;
284 memory-region = <&ipu_memory_regio 277 memory-region = <&ipu_memory_region>;
285 ti,timers = <&timer3>, <&timer4>; 278 ti,timers = <&timer3>, <&timer4>;
286 ti,watchdog-timers = <&timer9>, <& 279 ti,watchdog-timers = <&timer9>, <&timer11>;
287 clocks = <&ipu_clkctrl OMAP5_MMU_I 280 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
288 resets = <&prm_core 2>; 281 resets = <&prm_core 2>;
289 firmware-name = "omap5-ipu-fw.xem4 282 firmware-name = "omap5-ipu-fw.xem4";
290 }; 283 };
291 }; 284 };
292 285
293 - |+ 286 - |+
294 287
295 //Example 3: DRA7xx/AM57xx DSP 288 //Example 3: DRA7xx/AM57xx DSP
296 289
297 /* DSP1 Reserved Memory node */ 290 /* DSP1 Reserved Memory node */
298 #include <dt-bindings/clock/dra7.h> 291 #include <dt-bindings/clock/dra7.h>
299 reserved-memory { 292 reserved-memory {
300 #address-cells = <2>; 293 #address-cells = <2>;
301 #size-cells = <2>; 294 #size-cells = <2>;
302 295
303 dsp1_memory_region: dsp1-memory@990000 296 dsp1_memory_region: dsp1-memory@99000000 {
304 compatible = "shared-dma-pool"; 297 compatible = "shared-dma-pool";
305 reg = <0x0 0x99000000 0x0 0x400000 298 reg = <0x0 0x99000000 0x0 0x4000000>;
306 reusable; 299 reusable;
307 }; 300 };
308 }; 301 };
309 302
310 /* DSP1 node */ 303 /* DSP1 node */
311 ocp { 304 ocp {
312 #address-cells = <1>; 305 #address-cells = <1>;
313 #size-cells = <1>; 306 #size-cells = <1>;
314 307
315 dsp1: dsp@40800000 { 308 dsp1: dsp@40800000 {
316 compatible = "ti,dra7-dsp"; 309 compatible = "ti,dra7-dsp";
317 reg = <0x40800000 0x48000>, 310 reg = <0x40800000 0x48000>,
318 <0x40e00000 0x8000>, 311 <0x40e00000 0x8000>,
319 <0x40f00000 0x8000>; 312 <0x40f00000 0x8000>;
320 reg-names = "l2ram", "l1pram", "l1 313 reg-names = "l2ram", "l1pram", "l1dram";
321 ti,bootreg = <&scm_conf 0x55c 0>; 314 ti,bootreg = <&scm_conf 0x55c 0>;
322 iommus = <&mmu0_dsp1>, <&mmu1_dsp1 315 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
323 mboxes = <&mailbox5 &mbox_dsp1_ipc 316 mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
324 memory-region = <&dsp1_memory_regi 317 memory-region = <&dsp1_memory_region>;
325 ti,timers = <&timer5>; 318 ti,timers = <&timer5>;
326 ti,watchdog-timers = <&timer10>; 319 ti,watchdog-timers = <&timer10>;
327 resets = <&prm_dsp1 0>; 320 resets = <&prm_dsp1 0>;
328 clocks = <&dsp1_clkctrl DRA7_DSP1_ 321 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
329 firmware-name = "dra7-dsp1-fw.xe66 322 firmware-name = "dra7-dsp1-fw.xe66";
330 }; 323 };
331 }; 324 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.