1 # SPDX-License-Identifier: (GPL-2.0-only OR BS !! 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ 4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: OMAP4+ Remoteproc Devices 7 title: OMAP4+ Remoteproc Devices
8 8
9 maintainers: 9 maintainers:
10 - Suman Anna <s-anna@ti.com> 10 - Suman Anna <s-anna@ti.com>
11 11
12 description: 12 description:
13 The OMAP family of SoCs usually have one or 13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the process 14 that are used to offload some of the processor-intensive tasks, or to manage
15 other hardware accelerators, for achieving v 15 other hardware accelerators, for achieving various system level goals.
16 16
17 The processor cores in the sub-system are us 17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal 18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
19 caches, an Interrupt Controller, a Cache Con 19 caches, an Interrupt Controller, a Cache Controller etc.
20 20
21 The OMAP SoCs usually have a DSP processor s 21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
22 sub-system. The DSP processor sub-system can 22 sub-system. The DSP processor sub-system can contain any of the TI's C64x,
23 C66x or C67x family of DSP cores as the main 23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
24 sub-system usually contains either a Dual-Co 24 sub-system usually contains either a Dual-Core Cortex-M3 or Dual-Core
25 Cortex-M4 processors. 25 Cortex-M4 processors.
26 26
27 Each remote processor sub-system is represen 27 Each remote processor sub-system is represented as a single DT node. Each node
28 has a number of required or optional propert 28 has a number of required or optional properties that enable the OS running on
29 the host processor (MPU) to perform the devi 29 the host processor (MPU) to perform the device management of the remote
30 processor and to communicate with the remote 30 processor and to communicate with the remote processor. The various properties
31 can be classified as constant or variable. T 31 can be classified as constant or variable. The constant properties are
32 dictated by the SoC and does not change from 32 dictated by the SoC and does not change from one board to another having the
33 same SoC. Examples of constant properties in 33 same SoC. Examples of constant properties include 'iommus', 'reg'. The
34 variable properties are dictated by the syst 34 variable properties are dictated by the system integration aspects such as
35 memory on the board, or configuration used w 35 memory on the board, or configuration used within the corresponding firmware
36 image. Examples of variable properties inclu 36 image. Examples of variable properties include 'mboxes', 'memory-region',
37 'timers', 'watchdog-timers' etc. 37 'timers', 'watchdog-timers' etc.
38 38
39 properties: 39 properties:
40 compatible: 40 compatible:
41 enum: 41 enum:
42 - ti,omap4-dsp 42 - ti,omap4-dsp
43 - ti,omap5-dsp 43 - ti,omap5-dsp
44 - ti,dra7-dsp 44 - ti,dra7-dsp
45 - ti,omap4-ipu 45 - ti,omap4-ipu
46 - ti,omap5-ipu 46 - ti,omap5-ipu
47 - ti,dra7-ipu 47 - ti,dra7-ipu
48 48
49 iommus: 49 iommus:
50 minItems: 1 50 minItems: 1
51 maxItems: 2 51 maxItems: 2
52 description: | 52 description: |
53 phandles to OMAP IOMMU nodes, that need 53 phandles to OMAP IOMMU nodes, that need to be programmed
54 for this remote processor to access any 54 for this remote processor to access any external RAM memory or
55 other peripheral device address spaces. 55 other peripheral device address spaces. This property usually
56 has only a single phandle. Multiple phan 56 has only a single phandle. Multiple phandles are used only in
57 cases where the sub-system has different 57 cases where the sub-system has different ports for different
58 sub-modules within the processor sub-sys 58 sub-modules within the processor sub-system (eg: DRA7 DSPs),
59 and need the same programming in both th 59 and need the same programming in both the MMUs.
60 60
61 mboxes: 61 mboxes:
62 minItems: 1 62 minItems: 1
63 maxItems: 2 63 maxItems: 2
64 description: | 64 description: |
65 OMAP Mailbox specifier denoting the sub- 65 OMAP Mailbox specifier denoting the sub-mailbox, to be used for
66 communication with the remote processor. 66 communication with the remote processor. The specifier format is
67 as per the bindings, 67 as per the bindings,
68 Documentation/devicetree/bindings/mailbo 68 Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml
69 This property should match with the sub- 69 This property should match with the sub-mailbox node used in
70 the firmware image. 70 the firmware image.
71 71
72 clocks: 72 clocks:
73 maxItems: 1 73 maxItems: 1
74 description: | 74 description: |
75 Main functional clock for the remote pro 75 Main functional clock for the remote processor
76 76
77 resets: 77 resets:
78 minItems: 1 78 minItems: 1
79 maxItems: 2 79 maxItems: 2
80 description: | 80 description: |
81 Reset handles for the remote processor 81 Reset handles for the remote processor
82 82
83 firmware-name: 83 firmware-name:
84 description: | 84 description: |
85 Default name of the firmware to load to 85 Default name of the firmware to load to the remote processor.
86 86
87 # Optional properties: 87 # Optional properties:
88 # -------------------- 88 # --------------------
89 # Some of these properties are mandatory on so 89 # Some of these properties are mandatory on some SoCs, and some are optional
90 # depending on the configuration of the firmwa 90 # depending on the configuration of the firmware image to be executed on the
91 # remote processor. The conditions are mention 91 # remote processor. The conditions are mentioned for each property.
92 # 92 #
93 # The following are the optional properties: 93 # The following are the optional properties:
94 94
95 memory-region: 95 memory-region:
96 maxItems: 1 96 maxItems: 1
97 description: | 97 description: |
98 phandle to the reserved memory node to b 98 phandle to the reserved memory node to be associated
99 with the remoteproc device. The reserved 99 with the remoteproc device. The reserved memory node
100 can be a CMA memory node, and should be 100 can be a CMA memory node, and should be defined as
101 per the bindings, 101 per the bindings,
102 Documentation/devicetree/bindings/reserv 102 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
103 103
104 reg: 104 reg:
105 description: | 105 description: |
106 Address space for any remoteproc memorie 106 Address space for any remoteproc memories present on
107 the SoC. Should contain an entry for eac 107 the SoC. Should contain an entry for each value in
108 'reg-names'. These are mandatory for all 108 'reg-names'. These are mandatory for all DSP and IPU
109 processors that have them (OMAP4/OMAP5 D 109 processors that have them (OMAP4/OMAP5 DSPs do not have
110 any RAMs) 110 any RAMs)
111 111
112 reg-names: 112 reg-names:
113 description: | 113 description: |
114 Required names for each of the address s 114 Required names for each of the address spaces defined in
115 the 'reg' property. Expects the names fr 115 the 'reg' property. Expects the names from the following
116 list, in the specified order, each repre 116 list, in the specified order, each representing the corresponding
117 internal RAM memory region. 117 internal RAM memory region.
118 minItems: 1 118 minItems: 1
119 items: 119 items:
120 - const: l2ram 120 - const: l2ram
121 - const: l1pram 121 - const: l1pram
122 - const: l1dram 122 - const: l1dram
123 123
124 ti,bootreg: 124 ti,bootreg:
125 $ref: /schemas/types.yaml#/definitions/pha 125 $ref: /schemas/types.yaml#/definitions/phandle-array
126 items: 126 items:
127 - items: 127 - items:
128 - description: phandle to the System 128 - description: phandle to the System Control Configuration region
129 - description: register offset of th 129 - description: register offset of the boot address register
130 - description: the bit shift within 130 - description: the bit shift within the register
131 description: 131 description:
132 This property is required for all the DS 132 This property is required for all the DSP instances on OMAP4, OMAP5
133 and DRA7xx SoCs. 133 and DRA7xx SoCs.
134 134
135 ti,autosuspend-delay-ms: 135 ti,autosuspend-delay-ms:
136 description: | 136 description: |
137 Custom autosuspend delay for the remotep 137 Custom autosuspend delay for the remoteproc in milliseconds.
138 Recommended values is preferable to be i 138 Recommended values is preferable to be in the order of couple
139 of seconds. A negative value can also be 139 of seconds. A negative value can also be used to disable the
140 autosuspend behavior. 140 autosuspend behavior.
141 141
142 ti,timers: 142 ti,timers:
143 $ref: /schemas/types.yaml#/definitions/pha 143 $ref: /schemas/types.yaml#/definitions/phandle-array
144 items: 144 items:
145 maxItems: 1 145 maxItems: 1
146 description: | 146 description: |
147 One or more phandles to OMAP DMTimer nod 147 One or more phandles to OMAP DMTimer nodes, that serve
148 as System/Tick timers for the OS running 148 as System/Tick timers for the OS running on the remote
149 processors. This will usually be a singl 149 processors. This will usually be a single timer if the
150 processor sub-system is running in SMP m 150 processor sub-system is running in SMP mode, or one per
151 core in the processor sub-system. This c 151 core in the processor sub-system. This can also be used
152 to reserve specific timers to be dedicat 152 to reserve specific timers to be dedicated to the
153 remote processors. 153 remote processors.
154 154
155 This property is mandatory on remote pro 155 This property is mandatory on remote processors requiring
156 external tick wakeup, and to support Pow 156 external tick wakeup, and to support Power Management
157 features. The timers to be used should m 157 features. The timers to be used should match with the
158 timers used in the firmware image. 158 timers used in the firmware image.
159 159
160 ti,watchdog-timers: 160 ti,watchdog-timers:
161 $ref: /schemas/types.yaml#/definitions/pha 161 $ref: /schemas/types.yaml#/definitions/phandle-array
162 items: 162 items:
163 maxItems: 1 163 maxItems: 1
164 description: | 164 description: |
165 One or more phandles to OMAP DMTimer nod 165 One or more phandles to OMAP DMTimer nodes, used to
166 serve as Watchdog timers for the process 166 serve as Watchdog timers for the processor cores. This
167 will usually be one per executing proces 167 will usually be one per executing processor core, even
168 if the processor sub-system is running a 168 if the processor sub-system is running a SMP OS.
169 169
170 The timers to be used should match with 170 The timers to be used should match with the watchdog
171 timers used in the firmware image. 171 timers used in the firmware image.
172 172
173 if: 173 if:
174 properties: 174 properties:
175 compatible: 175 compatible:
176 enum: 176 enum:
177 - ti,dra7-dsp 177 - ti,dra7-dsp
178 then: 178 then:
179 properties: 179 properties:
180 reg: 180 reg:
181 minItems: 3 181 minItems: 3
182 maxItems: 3 182 maxItems: 3
183 required: 183 required:
184 - reg 184 - reg
185 - reg-names 185 - reg-names
186 - ti,bootreg 186 - ti,bootreg
187 187
188 else: 188 else:
189 if: 189 if:
190 properties: 190 properties:
191 compatible: 191 compatible:
192 enum: 192 enum:
193 - ti,omap4-ipu 193 - ti,omap4-ipu
194 - ti,omap5-ipu 194 - ti,omap5-ipu
195 - ti,dra7-ipu 195 - ti,dra7-ipu
196 then: 196 then:
197 properties: 197 properties:
198 reg: 198 reg:
199 minItems: 1 199 minItems: 1
200 maxItems: 1 200 maxItems: 1
201 ti,bootreg: false 201 ti,bootreg: false
202 required: 202 required:
203 - reg 203 - reg
204 - reg-names 204 - reg-names
205 205
206 else: 206 else:
207 properties: 207 properties:
208 reg: false 208 reg: false
209 required: 209 required:
210 - ti,bootreg 210 - ti,bootreg
211 211
212 required: 212 required:
213 - compatible 213 - compatible
214 - iommus 214 - iommus
215 - mboxes 215 - mboxes
216 - clocks 216 - clocks
217 - resets 217 - resets
218 - firmware-name 218 - firmware-name
219 219
220 additionalProperties: false 220 additionalProperties: false
221 221
222 examples: 222 examples:
223 - | 223 - |
224 224
225 //Example 1: OMAP4 DSP 225 //Example 1: OMAP4 DSP
226 226
227 /* DSP Reserved Memory node */ 227 /* DSP Reserved Memory node */
228 #include <dt-bindings/clock/omap4.h> 228 #include <dt-bindings/clock/omap4.h>
229 reserved-memory { 229 reserved-memory {
230 #address-cells = <1>; 230 #address-cells = <1>;
231 #size-cells = <1>; 231 #size-cells = <1>;
232 232
233 dsp_memory_region: dsp-memory@98000000 233 dsp_memory_region: dsp-memory@98000000 {
234 compatible = "shared-dma-pool"; 234 compatible = "shared-dma-pool";
235 reg = <0x98000000 0x800000>; 235 reg = <0x98000000 0x800000>;
236 reusable; 236 reusable;
237 }; 237 };
238 }; 238 };
239 239
240 /* DSP node */ 240 /* DSP node */
241 ocp { 241 ocp {
242 dsp: dsp { 242 dsp: dsp {
243 compatible = "ti,omap4-dsp"; 243 compatible = "ti,omap4-dsp";
244 ti,bootreg = <&scm_conf 0x304 0>; 244 ti,bootreg = <&scm_conf 0x304 0>;
245 iommus = <&mmu_dsp>; 245 iommus = <&mmu_dsp>;
246 mboxes = <&mailbox &mbox_dsp>; 246 mboxes = <&mailbox &mbox_dsp>;
247 memory-region = <&dsp_memory_regio 247 memory-region = <&dsp_memory_region>;
248 ti,timers = <&timer5>; 248 ti,timers = <&timer5>;
249 ti,watchdog-timers = <&timer6>; 249 ti,watchdog-timers = <&timer6>;
250 clocks = <&tesla_clkctrl OMAP4_DSP 250 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
251 resets = <&prm_tesla 0>, <&prm_tes 251 resets = <&prm_tesla 0>, <&prm_tesla 1>;
252 firmware-name = "omap4-dsp-fw.xe64 252 firmware-name = "omap4-dsp-fw.xe64T";
253 }; 253 };
254 }; 254 };
255 255
256 - |+ 256 - |+
257 257
258 //Example 2: OMAP5 IPU 258 //Example 2: OMAP5 IPU
259 259
260 /* IPU Reserved Memory node */ 260 /* IPU Reserved Memory node */
261 #include <dt-bindings/clock/omap5.h> 261 #include <dt-bindings/clock/omap5.h>
262 reserved-memory { 262 reserved-memory {
263 #address-cells = <2>; 263 #address-cells = <2>;
264 #size-cells = <2>; 264 #size-cells = <2>;
265 265
266 ipu_memory_region: ipu-memory@95800000 266 ipu_memory_region: ipu-memory@95800000 {
267 compatible = "shared-dma-pool"; 267 compatible = "shared-dma-pool";
268 reg = <0 0x95800000 0 0x3800000>; 268 reg = <0 0x95800000 0 0x3800000>;
269 reusable; 269 reusable;
270 }; 270 };
271 }; 271 };
272 272
273 /* IPU node */ 273 /* IPU node */
274 ocp { 274 ocp {
275 #address-cells = <1>; 275 #address-cells = <1>;
276 #size-cells = <1>; 276 #size-cells = <1>;
277 277
278 ipu: ipu@55020000 { 278 ipu: ipu@55020000 {
279 compatible = "ti,omap5-ipu"; 279 compatible = "ti,omap5-ipu";
280 reg = <0x55020000 0x10000>; 280 reg = <0x55020000 0x10000>;
281 reg-names = "l2ram"; 281 reg-names = "l2ram";
282 iommus = <&mmu_ipu>; 282 iommus = <&mmu_ipu>;
283 mboxes = <&mailbox &mbox_ipu>; 283 mboxes = <&mailbox &mbox_ipu>;
284 memory-region = <&ipu_memory_regio 284 memory-region = <&ipu_memory_region>;
285 ti,timers = <&timer3>, <&timer4>; 285 ti,timers = <&timer3>, <&timer4>;
286 ti,watchdog-timers = <&timer9>, <& 286 ti,watchdog-timers = <&timer9>, <&timer11>;
287 clocks = <&ipu_clkctrl OMAP5_MMU_I 287 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
288 resets = <&prm_core 2>; 288 resets = <&prm_core 2>;
289 firmware-name = "omap5-ipu-fw.xem4 289 firmware-name = "omap5-ipu-fw.xem4";
290 }; 290 };
291 }; 291 };
292 292
293 - |+ 293 - |+
294 294
295 //Example 3: DRA7xx/AM57xx DSP 295 //Example 3: DRA7xx/AM57xx DSP
296 296
297 /* DSP1 Reserved Memory node */ 297 /* DSP1 Reserved Memory node */
298 #include <dt-bindings/clock/dra7.h> 298 #include <dt-bindings/clock/dra7.h>
299 reserved-memory { 299 reserved-memory {
300 #address-cells = <2>; 300 #address-cells = <2>;
301 #size-cells = <2>; 301 #size-cells = <2>;
302 302
303 dsp1_memory_region: dsp1-memory@990000 303 dsp1_memory_region: dsp1-memory@99000000 {
304 compatible = "shared-dma-pool"; 304 compatible = "shared-dma-pool";
305 reg = <0x0 0x99000000 0x0 0x400000 305 reg = <0x0 0x99000000 0x0 0x4000000>;
306 reusable; 306 reusable;
307 }; 307 };
308 }; 308 };
309 309
310 /* DSP1 node */ 310 /* DSP1 node */
311 ocp { 311 ocp {
312 #address-cells = <1>; 312 #address-cells = <1>;
313 #size-cells = <1>; 313 #size-cells = <1>;
314 314
315 dsp1: dsp@40800000 { 315 dsp1: dsp@40800000 {
316 compatible = "ti,dra7-dsp"; 316 compatible = "ti,dra7-dsp";
317 reg = <0x40800000 0x48000>, 317 reg = <0x40800000 0x48000>,
318 <0x40e00000 0x8000>, 318 <0x40e00000 0x8000>,
319 <0x40f00000 0x8000>; 319 <0x40f00000 0x8000>;
320 reg-names = "l2ram", "l1pram", "l1 320 reg-names = "l2ram", "l1pram", "l1dram";
321 ti,bootreg = <&scm_conf 0x55c 0>; 321 ti,bootreg = <&scm_conf 0x55c 0>;
322 iommus = <&mmu0_dsp1>, <&mmu1_dsp1 322 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
323 mboxes = <&mailbox5 &mbox_dsp1_ipc 323 mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
324 memory-region = <&dsp1_memory_regi 324 memory-region = <&dsp1_memory_region>;
325 ti,timers = <&timer5>; 325 ti,timers = <&timer5>;
326 ti,watchdog-timers = <&timer10>; 326 ti,watchdog-timers = <&timer10>;
327 resets = <&prm_dsp1 0>; 327 resets = <&prm_dsp1 0>;
328 clocks = <&dsp1_clkctrl DRA7_DSP1_ 328 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
329 firmware-name = "dra7-dsp1-fw.xe66 329 firmware-name = "dra7-dsp1-fw.xe66";
330 }; 330 };
331 }; 331 };
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