1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/riscv/cpus. 4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: RISC-V CPUs !! 7 title: RISC-V bindings for 'cpus' DT nodes
8 8
9 maintainers: 9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com> 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org> <<
13 12
14 description: | 13 description: |
15 This document uses some terminology common t 14 This document uses some terminology common to the RISC-V community
16 that is not widely used, the definitions of 15 that is not widely used, the definitions of which are listed here:
17 16
18 hart: A hardware execution context, which co 17 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some re 18 mandated by the RISC-V ISA: a PC and some registers. This
20 terminology is designed to disambiguate soft 19 terminology is designed to disambiguate software's view of execution
21 contexts from any particular microarchitectu 20 contexts from any particular microarchitectural implementation
22 strategy. For example, an Intel laptop cont 21 strategy. For example, an Intel laptop containing one socket with
23 two cores, each of which has two hyperthread 22 two cores, each of which has two hyperthreads, could be described as
24 having four harts. 23 having four harts.
25 24
26 allOf: <<
27 - $ref: /schemas/cpu.yaml# <<
28 - $ref: extensions.yaml <<
29 <<
30 properties: 25 properties:
31 compatible: 26 compatible:
32 oneOf: 27 oneOf:
33 - items: 28 - items:
34 - enum: 29 - enum:
35 - amd,mbv32 !! 30 - sifive,rocket0
36 - andestech,ax45mp <<
37 - canaan,k210 <<
38 - sifive,bullet0 31 - sifive,bullet0
39 - sifive,e5 32 - sifive,e5
40 - sifive,e7 33 - sifive,e7
>> 34 - sifive,e51
41 - sifive,e71 35 - sifive,e71
42 - sifive,rocket0 !! 36 - sifive,u54-mc
43 - sifive,s7 !! 37 - sifive,u74-mc
44 - sifive,u5 <<
45 - sifive,u54 38 - sifive,u54
46 - sifive,u7 <<
47 - sifive,u74 39 - sifive,u74
48 - sifive,u74-mc !! 40 - sifive,u5
49 - thead,c906 !! 41 - sifive,u7
50 - thead,c908 !! 42 - canaan,k210
51 - thead,c910 <<
52 - thead,c920 <<
53 - const: riscv <<
54 - items: <<
55 - enum: <<
56 - sifive,e51 <<
57 - sifive,u54-mc <<
58 - const: sifive,rocket0 <<
59 - const: riscv 43 - const: riscv
60 - const: riscv # Simulator only 44 - const: riscv # Simulator only
61 description: 45 description:
62 Identifies that the hart uses the RISC-V 46 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart. 47 and identifies the type of the hart.
64 48
65 mmu-type: 49 mmu-type:
66 description: 50 description:
67 Identifies the largest MMU address trans !! 51 Identifies the MMU address translation mode used on this
68 this hart. These values originate from !! 52 hart. These values originate from the RISC-V Privileged
69 Specification document, available from 53 Specification document, available from
70 https://riscv.org/specifications/ 54 https://riscv.org/specifications/
71 $ref: /schemas/types.yaml#/definitions/str !! 55 $ref: "/schemas/types.yaml#/definitions/string"
72 enum: 56 enum:
73 - riscv,sv32 57 - riscv,sv32
74 - riscv,sv39 58 - riscv,sv39
75 - riscv,sv48 59 - riscv,sv48
76 - riscv,sv57 <<
77 - riscv,none 60 - riscv,none
78 61
79 reg: !! 62 riscv,isa:
80 description: <<
81 The hart ID of this CPU node. <<
82 <<
83 riscv,cbom-block-size: <<
84 $ref: /schemas/types.yaml#/definitions/uin <<
85 description: 63 description:
86 The blocksize in bytes for the Zicbom ca !! 64 Identifies the specific RISC-V instruction set architecture
87 !! 65 supported by the hart. These are documented in the RISC-V
88 riscv,cbop-block-size: !! 66 User-Level ISA document, available from
89 $ref: /schemas/types.yaml#/definitions/uin !! 67 https://riscv.org/specifications/
90 description: <<
91 The blocksize in bytes for the Zicbop ca <<
92 68
93 riscv,cboz-block-size: !! 69 While the isa strings in ISA specification are case
94 $ref: /schemas/types.yaml#/definitions/uin !! 70 insensitive, letters in the riscv,isa string must be all
95 description: !! 71 lowercase to simplify parsing.
96 The blocksize in bytes for the Zicboz ca !! 72 $ref: "/schemas/types.yaml#/definitions/string"
>> 73 enum:
>> 74 - rv64imac
>> 75 - rv64imafdc
97 76
98 # RISC-V has multiple properties for cache o <<
99 # differ between individual CBO extensions <<
100 cache-op-block-size: false <<
101 # RISC-V requires 'timebase-frequency' in /c 77 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
102 timebase-frequency: false 78 timebase-frequency: false
103 79
104 interrupt-controller: 80 interrupt-controller:
105 type: object 81 type: object
106 $ref: /schemas/interrupt-controller/riscv, !! 82 description: Describes the CPU's local interrupt controller
107 83
108 cpu-idle-states: !! 84 properties:
109 $ref: /schemas/types.yaml#/definitions/pha !! 85 '#interrupt-cells':
110 items: !! 86 const: 1
111 maxItems: 1 <<
112 description: | <<
113 List of phandles to idle state nodes sup <<
114 by this hart (see ./idle-states.yaml). <<
115 87
116 capacity-dmips-mhz: !! 88 compatible:
117 description: !! 89 const: riscv,cpu-intc
118 u32 value representing CPU capacity (see !! 90
119 DMIPS/MHz, relative to highest capacity- !! 91 interrupt-controller: true
120 in the system. !! 92
121 !! 93 required:
122 anyOf: !! 94 - '#interrupt-cells'
123 - required: !! 95 - compatible
124 - riscv,isa !! 96 - interrupt-controller
125 - required: <<
126 - riscv,isa-base <<
127 <<
128 dependencies: <<
129 riscv,isa-base: [ "riscv,isa-extensions" ] <<
130 riscv,isa-extensions: [ "riscv,isa-base" ] <<
131 97
132 required: 98 required:
>> 99 - riscv,isa
133 - interrupt-controller 100 - interrupt-controller
134 101
135 unevaluatedProperties: false !! 102 additionalProperties: true
136 103
137 examples: 104 examples:
138 - | 105 - |
139 // Example 1: SiFive Freedom U540G Develop 106 // Example 1: SiFive Freedom U540G Development Kit
140 cpus { 107 cpus {
141 #address-cells = <1>; 108 #address-cells = <1>;
142 #size-cells = <0>; 109 #size-cells = <0>;
143 timebase-frequency = <1000000>; 110 timebase-frequency = <1000000>;
144 cpu@0 { 111 cpu@0 {
145 clock-frequency = <0>; 112 clock-frequency = <0>;
146 compatible = "sifive,rocket0", 113 compatible = "sifive,rocket0", "riscv";
147 device_type = "cpu"; 114 device_type = "cpu";
148 i-cache-block-size = <64>; 115 i-cache-block-size = <64>;
149 i-cache-sets = <128>; 116 i-cache-sets = <128>;
150 i-cache-size = <16384>; 117 i-cache-size = <16384>;
151 reg = <0>; 118 reg = <0>;
152 riscv,isa-base = "rv64i"; !! 119 riscv,isa = "rv64imac";
153 riscv,isa-extensions = "i", "m <<
154 <<
155 cpu_intc0: interrupt-controlle 120 cpu_intc0: interrupt-controller {
156 #interrupt-cells = <1> 121 #interrupt-cells = <1>;
157 compatible = "riscv,cp 122 compatible = "riscv,cpu-intc";
158 interrupt-controller; 123 interrupt-controller;
159 }; 124 };
160 }; 125 };
161 cpu@1 { 126 cpu@1 {
162 clock-frequency = <0>; 127 clock-frequency = <0>;
163 compatible = "sifive,rocket0", 128 compatible = "sifive,rocket0", "riscv";
164 d-cache-block-size = <64>; 129 d-cache-block-size = <64>;
165 d-cache-sets = <64>; 130 d-cache-sets = <64>;
166 d-cache-size = <32768>; 131 d-cache-size = <32768>;
167 d-tlb-sets = <1>; 132 d-tlb-sets = <1>;
168 d-tlb-size = <32>; 133 d-tlb-size = <32>;
169 device_type = "cpu"; 134 device_type = "cpu";
170 i-cache-block-size = <64>; 135 i-cache-block-size = <64>;
171 i-cache-sets = <64>; 136 i-cache-sets = <64>;
172 i-cache-size = <32768>; 137 i-cache-size = <32768>;
173 i-tlb-sets = <1>; 138 i-tlb-sets = <1>;
174 i-tlb-size = <32>; 139 i-tlb-size = <32>;
175 mmu-type = "riscv,sv39"; 140 mmu-type = "riscv,sv39";
176 reg = <1>; 141 reg = <1>;
>> 142 riscv,isa = "rv64imafdc";
177 tlb-split; 143 tlb-split;
178 riscv,isa-base = "rv64i"; <<
179 riscv,isa-extensions = "i", "m <<
180 <<
181 cpu_intc1: interrupt-controlle 144 cpu_intc1: interrupt-controller {
182 #interrupt-cells = <1> 145 #interrupt-cells = <1>;
183 compatible = "riscv,cp 146 compatible = "riscv,cpu-intc";
184 interrupt-controller; 147 interrupt-controller;
185 }; 148 };
186 }; 149 };
187 }; 150 };
188 151
189 - | 152 - |
190 // Example 2: Spike ISA Simulator with 1 H 153 // Example 2: Spike ISA Simulator with 1 Hart
191 cpus { 154 cpus {
192 #address-cells = <1>; 155 #address-cells = <1>;
193 #size-cells = <0>; 156 #size-cells = <0>;
194 cpu@0 { 157 cpu@0 {
195 device_type = "cpu"; 158 device_type = "cpu";
196 reg = <0>; 159 reg = <0>;
197 compatible = "riscv"; 160 compatible = "riscv";
>> 161 riscv,isa = "rv64imafdc";
198 mmu-type = "riscv,sv48"; 162 mmu-type = "riscv,sv48";
199 riscv,isa-base = "rv64i"; <<
200 riscv,isa-extensions = "i", "m <<
201 <<
202 interrupt-controller { 163 interrupt-controller {
203 #interrupt-cells = <1> 164 #interrupt-cells = <1>;
204 interrupt-controller; 165 interrupt-controller;
205 compatible = "riscv,cp 166 compatible = "riscv,cpu-intc";
206 }; 167 };
207 }; 168 };
208 }; 169 };
209 ... 170 ...
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.