1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/riscv/cpus. 4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: RISC-V CPUs !! 7 title: RISC-V bindings for 'cpus' DT nodes
8 8
9 maintainers: 9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com> 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org> <<
13 12
14 description: | 13 description: |
15 This document uses some terminology common t 14 This document uses some terminology common to the RISC-V community
16 that is not widely used, the definitions of 15 that is not widely used, the definitions of which are listed here:
17 16
18 hart: A hardware execution context, which co 17 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some re 18 mandated by the RISC-V ISA: a PC and some registers. This
20 terminology is designed to disambiguate soft 19 terminology is designed to disambiguate software's view of execution
21 contexts from any particular microarchitectu 20 contexts from any particular microarchitectural implementation
22 strategy. For example, an Intel laptop cont 21 strategy. For example, an Intel laptop containing one socket with
23 two cores, each of which has two hyperthread 22 two cores, each of which has two hyperthreads, could be described as
24 having four harts. 23 having four harts.
25 24
26 allOf: <<
27 - $ref: /schemas/cpu.yaml# <<
28 - $ref: extensions.yaml <<
29 <<
30 properties: 25 properties:
31 compatible: 26 compatible:
32 oneOf: 27 oneOf:
33 - items: 28 - items:
34 - enum: 29 - enum:
35 - amd,mbv32 !! 30 - sifive,rocket0
36 - andestech,ax45mp <<
37 - canaan,k210 <<
38 - sifive,bullet0 31 - sifive,bullet0
39 - sifive,e5 32 - sifive,e5
40 - sifive,e7 33 - sifive,e7
41 - sifive,e71 34 - sifive,e71
42 - sifive,rocket0 !! 35 - sifive,u74-mc
43 - sifive,s7 <<
44 - sifive,u5 <<
45 - sifive,u54 36 - sifive,u54
46 - sifive,u7 <<
47 - sifive,u74 37 - sifive,u74
48 - sifive,u74-mc !! 38 - sifive,u5
49 - thead,c906 !! 39 - sifive,u7
50 - thead,c908 !! 40 - canaan,k210
51 - thead,c910 <<
52 - thead,c920 <<
53 - const: riscv 41 - const: riscv
54 - items: 42 - items:
55 - enum: 43 - enum:
56 - sifive,e51 44 - sifive,e51
57 - sifive,u54-mc 45 - sifive,u54-mc
58 - const: sifive,rocket0 46 - const: sifive,rocket0
59 - const: riscv 47 - const: riscv
60 - const: riscv # Simulator only 48 - const: riscv # Simulator only
61 description: 49 description:
62 Identifies that the hart uses the RISC-V 50 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart. 51 and identifies the type of the hart.
64 52
65 mmu-type: 53 mmu-type:
66 description: 54 description:
67 Identifies the largest MMU address trans !! 55 Identifies the MMU address translation mode used on this
68 this hart. These values originate from !! 56 hart. These values originate from the RISC-V Privileged
69 Specification document, available from 57 Specification document, available from
70 https://riscv.org/specifications/ 58 https://riscv.org/specifications/
71 $ref: /schemas/types.yaml#/definitions/str !! 59 $ref: "/schemas/types.yaml#/definitions/string"
72 enum: 60 enum:
73 - riscv,sv32 61 - riscv,sv32
74 - riscv,sv39 62 - riscv,sv39
75 - riscv,sv48 63 - riscv,sv48
76 - riscv,sv57 <<
77 - riscv,none 64 - riscv,none
78 65
79 reg: !! 66 riscv,isa:
80 description: 67 description:
81 The hart ID of this CPU node. !! 68 Identifies the specific RISC-V instruction set architecture
82 !! 69 supported by the hart. These are documented in the RISC-V
83 riscv,cbom-block-size: !! 70 User-Level ISA document, available from
84 $ref: /schemas/types.yaml#/definitions/uin !! 71 https://riscv.org/specifications/
85 description: <<
86 The blocksize in bytes for the Zicbom ca <<
87 <<
88 riscv,cbop-block-size: <<
89 $ref: /schemas/types.yaml#/definitions/uin <<
90 description: <<
91 The blocksize in bytes for the Zicbop ca <<
92 72
93 riscv,cboz-block-size: !! 73 While the isa strings in ISA specification are case
94 $ref: /schemas/types.yaml#/definitions/uin !! 74 insensitive, letters in the riscv,isa string must be all
95 description: !! 75 lowercase to simplify parsing.
96 The blocksize in bytes for the Zicboz ca !! 76 $ref: "/schemas/types.yaml#/definitions/string"
>> 77 enum:
>> 78 - rv64imac
>> 79 - rv64imafdc
97 80
98 # RISC-V has multiple properties for cache o <<
99 # differ between individual CBO extensions <<
100 cache-op-block-size: false <<
101 # RISC-V requires 'timebase-frequency' in /c 81 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
102 timebase-frequency: false 82 timebase-frequency: false
103 83
104 interrupt-controller: 84 interrupt-controller:
105 type: object 85 type: object
106 $ref: /schemas/interrupt-controller/riscv, !! 86 description: Describes the CPU's local interrupt controller
>> 87
>> 88 properties:
>> 89 '#interrupt-cells':
>> 90 const: 1
>> 91
>> 92 compatible:
>> 93 const: riscv,cpu-intc
>> 94
>> 95 interrupt-controller: true
>> 96
>> 97 required:
>> 98 - '#interrupt-cells'
>> 99 - compatible
>> 100 - interrupt-controller
107 101
108 cpu-idle-states: 102 cpu-idle-states:
109 $ref: /schemas/types.yaml#/definitions/pha !! 103 $ref: '/schemas/types.yaml#/definitions/phandle-array'
110 items: 104 items:
111 maxItems: 1 105 maxItems: 1
112 description: | 106 description: |
113 List of phandles to idle state nodes sup 107 List of phandles to idle state nodes supported
114 by this hart (see ./idle-states.yaml). 108 by this hart (see ./idle-states.yaml).
115 109
116 capacity-dmips-mhz: <<
117 description: <<
118 u32 value representing CPU capacity (see <<
119 DMIPS/MHz, relative to highest capacity- <<
120 in the system. <<
121 <<
122 anyOf: <<
123 - required: <<
124 - riscv,isa <<
125 - required: <<
126 - riscv,isa-base <<
127 <<
128 dependencies: <<
129 riscv,isa-base: [ "riscv,isa-extensions" ] <<
130 riscv,isa-extensions: [ "riscv,isa-base" ] <<
131 <<
132 required: 110 required:
>> 111 - riscv,isa
133 - interrupt-controller 112 - interrupt-controller
134 113
135 unevaluatedProperties: false !! 114 additionalProperties: true
136 115
137 examples: 116 examples:
138 - | 117 - |
139 // Example 1: SiFive Freedom U540G Develop 118 // Example 1: SiFive Freedom U540G Development Kit
140 cpus { 119 cpus {
141 #address-cells = <1>; 120 #address-cells = <1>;
142 #size-cells = <0>; 121 #size-cells = <0>;
143 timebase-frequency = <1000000>; 122 timebase-frequency = <1000000>;
144 cpu@0 { 123 cpu@0 {
145 clock-frequency = <0>; 124 clock-frequency = <0>;
146 compatible = "sifive,rocket0", 125 compatible = "sifive,rocket0", "riscv";
147 device_type = "cpu"; 126 device_type = "cpu";
148 i-cache-block-size = <64>; 127 i-cache-block-size = <64>;
149 i-cache-sets = <128>; 128 i-cache-sets = <128>;
150 i-cache-size = <16384>; 129 i-cache-size = <16384>;
151 reg = <0>; 130 reg = <0>;
152 riscv,isa-base = "rv64i"; !! 131 riscv,isa = "rv64imac";
153 riscv,isa-extensions = "i", "m <<
154 <<
155 cpu_intc0: interrupt-controlle 132 cpu_intc0: interrupt-controller {
156 #interrupt-cells = <1> 133 #interrupt-cells = <1>;
157 compatible = "riscv,cp 134 compatible = "riscv,cpu-intc";
158 interrupt-controller; 135 interrupt-controller;
159 }; 136 };
160 }; 137 };
161 cpu@1 { 138 cpu@1 {
162 clock-frequency = <0>; 139 clock-frequency = <0>;
163 compatible = "sifive,rocket0", 140 compatible = "sifive,rocket0", "riscv";
164 d-cache-block-size = <64>; 141 d-cache-block-size = <64>;
165 d-cache-sets = <64>; 142 d-cache-sets = <64>;
166 d-cache-size = <32768>; 143 d-cache-size = <32768>;
167 d-tlb-sets = <1>; 144 d-tlb-sets = <1>;
168 d-tlb-size = <32>; 145 d-tlb-size = <32>;
169 device_type = "cpu"; 146 device_type = "cpu";
170 i-cache-block-size = <64>; 147 i-cache-block-size = <64>;
171 i-cache-sets = <64>; 148 i-cache-sets = <64>;
172 i-cache-size = <32768>; 149 i-cache-size = <32768>;
173 i-tlb-sets = <1>; 150 i-tlb-sets = <1>;
174 i-tlb-size = <32>; 151 i-tlb-size = <32>;
175 mmu-type = "riscv,sv39"; 152 mmu-type = "riscv,sv39";
176 reg = <1>; 153 reg = <1>;
>> 154 riscv,isa = "rv64imafdc";
177 tlb-split; 155 tlb-split;
178 riscv,isa-base = "rv64i"; <<
179 riscv,isa-extensions = "i", "m <<
180 <<
181 cpu_intc1: interrupt-controlle 156 cpu_intc1: interrupt-controller {
182 #interrupt-cells = <1> 157 #interrupt-cells = <1>;
183 compatible = "riscv,cp 158 compatible = "riscv,cpu-intc";
184 interrupt-controller; 159 interrupt-controller;
185 }; 160 };
186 }; 161 };
187 }; 162 };
188 163
189 - | 164 - |
190 // Example 2: Spike ISA Simulator with 1 H 165 // Example 2: Spike ISA Simulator with 1 Hart
191 cpus { 166 cpus {
192 #address-cells = <1>; 167 #address-cells = <1>;
193 #size-cells = <0>; 168 #size-cells = <0>;
194 cpu@0 { 169 cpu@0 {
195 device_type = "cpu"; 170 device_type = "cpu";
196 reg = <0>; 171 reg = <0>;
197 compatible = "riscv"; 172 compatible = "riscv";
>> 173 riscv,isa = "rv64imafdc";
198 mmu-type = "riscv,sv48"; 174 mmu-type = "riscv,sv48";
199 riscv,isa-base = "rv64i"; <<
200 riscv,isa-extensions = "i", "m <<
201 <<
202 interrupt-controller { 175 interrupt-controller {
203 #interrupt-cells = <1> 176 #interrupt-cells = <1>;
204 interrupt-controller; 177 interrupt-controller;
205 compatible = "riscv,cp 178 compatible = "riscv,cpu-intc";
206 }; 179 };
207 }; 180 };
208 }; 181 };
209 ... 182 ...
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.