1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/riscv/cpus. 4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: RISC-V CPUs !! 7 title: RISC-V bindings for 'cpus' DT nodes
8 8
9 maintainers: 9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com> 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org> <<
13 <<
14 description: | <<
15 This document uses some terminology common t <<
16 that is not widely used, the definitions of <<
17 <<
18 hart: A hardware execution context, which co <<
19 mandated by the RISC-V ISA: a PC and some re <<
20 terminology is designed to disambiguate soft <<
21 contexts from any particular microarchitectu <<
22 strategy. For example, an Intel laptop cont <<
23 two cores, each of which has two hyperthread <<
24 having four harts. <<
25 12
26 allOf: 13 allOf:
27 - $ref: /schemas/cpu.yaml# !! 14 - $ref: /schemas/cpus.yaml#
28 - $ref: extensions.yaml <<
29 15
30 properties: 16 properties:
31 compatible: !! 17 $nodename:
32 oneOf: !! 18 const: cpus
33 - items: !! 19 description: Container of cpu nodes
>> 20
>> 21 '#address-cells':
>> 22 const: 1
>> 23 description: |
>> 24 A single unsigned 32-bit integer uniquely identifies each RISC-V
>> 25 hart in a system. (See the "reg" node under the "cpu" node,
>> 26 below).
>> 27
>> 28 '#size-cells':
>> 29 const: 0
>> 30
>> 31 patternProperties:
>> 32 '^cpu@[0-9a-f]+$':
>> 33 properties:
>> 34 compatible:
>> 35 type: array
>> 36 items:
34 - enum: 37 - enum:
35 - amd,mbv32 <<
36 - andestech,ax45mp <<
37 - canaan,k210 <<
38 - sifive,bullet0 <<
39 - sifive,e5 <<
40 - sifive,e7 <<
41 - sifive,e71 <<
42 - sifive,rocket0 38 - sifive,rocket0
43 - sifive,s7 !! 39 - sifive,e5
44 - sifive,u5 <<
45 - sifive,u54 <<
46 - sifive,u7 <<
47 - sifive,u74 <<
48 - sifive,u74-mc <<
49 - thead,c906 <<
50 - thead,c908 <<
51 - thead,c910 <<
52 - thead,c920 <<
53 - const: riscv <<
54 - items: <<
55 - enum: <<
56 - sifive,e51 40 - sifive,e51
57 - sifive,u54-mc 41 - sifive,u54-mc
58 - const: sifive,rocket0 !! 42 - sifive,u54
>> 43 - sifive,u5
59 - const: riscv 44 - const: riscv
60 - const: riscv # Simulator only !! 45 description:
61 description: !! 46 Identifies that the hart uses the RISC-V instruction set
62 Identifies that the hart uses the RISC-V !! 47 and identifies the type of the hart.
63 and identifies the type of the hart. !! 48
64 !! 49 mmu-type:
65 mmu-type: !! 50 allOf:
66 description: !! 51 - $ref: "/schemas/types.yaml#/definitions/string"
67 Identifies the largest MMU address trans !! 52 - enum:
68 this hart. These values originate from !! 53 - riscv,sv32
69 Specification document, available from !! 54 - riscv,sv39
70 https://riscv.org/specifications/ !! 55 - riscv,sv48
71 $ref: /schemas/types.yaml#/definitions/str !! 56 description:
72 enum: !! 57 Identifies the MMU address translation mode used on this
73 - riscv,sv32 !! 58 hart. These values originate from the RISC-V Privileged
74 - riscv,sv39 !! 59 Specification document, available from
75 - riscv,sv48 !! 60 https://riscv.org/specifications/
76 - riscv,sv57 !! 61
77 - riscv,none !! 62 riscv,isa:
78 !! 63 allOf:
79 reg: !! 64 - $ref: "/schemas/types.yaml#/definitions/string"
80 description: !! 65 - enum:
81 The hart ID of this CPU node. !! 66 - rv64imac
82 !! 67 - rv64imafdc
83 riscv,cbom-block-size: !! 68 description:
84 $ref: /schemas/types.yaml#/definitions/uin !! 69 Identifies the specific RISC-V instruction set architecture
85 description: !! 70 supported by the hart. These are documented in the RISC-V
86 The blocksize in bytes for the Zicbom ca !! 71 User-Level ISA document, available from
87 !! 72 https://riscv.org/specifications/
88 riscv,cbop-block-size: !! 73
89 $ref: /schemas/types.yaml#/definitions/uin !! 74 timebase-frequency:
90 description: !! 75 type: integer
91 The blocksize in bytes for the Zicbop ca !! 76 minimum: 1
92 !! 77 description:
93 riscv,cboz-block-size: !! 78 Specifies the clock frequency of the system timer in Hz.
94 $ref: /schemas/types.yaml#/definitions/uin !! 79 This value is common to all harts on a single system image.
95 description: !! 80
96 The blocksize in bytes for the Zicboz ca !! 81 interrupt-controller:
97 !! 82 type: object
98 # RISC-V has multiple properties for cache o !! 83 description: Describes the CPU's local interrupt controller
99 # differ between individual CBO extensions !! 84
100 cache-op-block-size: false !! 85 properties:
101 # RISC-V requires 'timebase-frequency' in /c !! 86 '#interrupt-cells':
102 timebase-frequency: false !! 87 const: 1
103 !! 88
104 interrupt-controller: !! 89 compatible:
105 type: object !! 90 const: riscv,cpu-intc
106 $ref: /schemas/interrupt-controller/riscv, !! 91
107 !! 92 interrupt-controller: true
108 cpu-idle-states: !! 93
109 $ref: /schemas/types.yaml#/definitions/pha !! 94 required:
110 items: !! 95 - '#interrupt-cells'
111 maxItems: 1 !! 96 - compatible
112 description: | !! 97 - interrupt-controller
113 List of phandles to idle state nodes sup <<
114 by this hart (see ./idle-states.yaml). <<
115 <<
116 capacity-dmips-mhz: <<
117 description: <<
118 u32 value representing CPU capacity (see <<
119 DMIPS/MHz, relative to highest capacity- <<
120 in the system. <<
121 98
122 anyOf: !! 99 required:
123 - required: <<
124 - riscv,isa 100 - riscv,isa
125 - required: !! 101 - timebase-frequency
126 - riscv,isa-base !! 102 - interrupt-controller
127 <<
128 dependencies: <<
129 riscv,isa-base: [ "riscv,isa-extensions" ] <<
130 riscv,isa-extensions: [ "riscv,isa-base" ] <<
131 <<
132 required: <<
133 - interrupt-controller <<
134 <<
135 unevaluatedProperties: false <<
136 103
137 examples: 104 examples:
138 - | 105 - |
139 // Example 1: SiFive Freedom U540G Develop 106 // Example 1: SiFive Freedom U540G Development Kit
140 cpus { 107 cpus {
141 #address-cells = <1>; 108 #address-cells = <1>;
142 #size-cells = <0>; 109 #size-cells = <0>;
143 timebase-frequency = <1000000>; 110 timebase-frequency = <1000000>;
144 cpu@0 { 111 cpu@0 {
145 clock-frequency = <0>; 112 clock-frequency = <0>;
146 compatible = "sifive,rocket0", 113 compatible = "sifive,rocket0", "riscv";
147 device_type = "cpu"; 114 device_type = "cpu";
148 i-cache-block-size = <64>; 115 i-cache-block-size = <64>;
149 i-cache-sets = <128>; 116 i-cache-sets = <128>;
150 i-cache-size = <16384>; 117 i-cache-size = <16384>;
151 reg = <0>; 118 reg = <0>;
152 riscv,isa-base = "rv64i"; !! 119 riscv,isa = "rv64imac";
153 riscv,isa-extensions = "i", "m <<
154 <<
155 cpu_intc0: interrupt-controlle 120 cpu_intc0: interrupt-controller {
156 #interrupt-cells = <1> 121 #interrupt-cells = <1>;
157 compatible = "riscv,cp 122 compatible = "riscv,cpu-intc";
158 interrupt-controller; 123 interrupt-controller;
159 }; 124 };
160 }; 125 };
161 cpu@1 { 126 cpu@1 {
162 clock-frequency = <0>; 127 clock-frequency = <0>;
163 compatible = "sifive,rocket0", 128 compatible = "sifive,rocket0", "riscv";
164 d-cache-block-size = <64>; 129 d-cache-block-size = <64>;
165 d-cache-sets = <64>; 130 d-cache-sets = <64>;
166 d-cache-size = <32768>; 131 d-cache-size = <32768>;
167 d-tlb-sets = <1>; 132 d-tlb-sets = <1>;
168 d-tlb-size = <32>; 133 d-tlb-size = <32>;
169 device_type = "cpu"; 134 device_type = "cpu";
170 i-cache-block-size = <64>; 135 i-cache-block-size = <64>;
171 i-cache-sets = <64>; 136 i-cache-sets = <64>;
172 i-cache-size = <32768>; 137 i-cache-size = <32768>;
173 i-tlb-sets = <1>; 138 i-tlb-sets = <1>;
174 i-tlb-size = <32>; 139 i-tlb-size = <32>;
175 mmu-type = "riscv,sv39"; 140 mmu-type = "riscv,sv39";
176 reg = <1>; 141 reg = <1>;
>> 142 riscv,isa = "rv64imafdc";
177 tlb-split; 143 tlb-split;
178 riscv,isa-base = "rv64i"; <<
179 riscv,isa-extensions = "i", "m <<
180 <<
181 cpu_intc1: interrupt-controlle 144 cpu_intc1: interrupt-controller {
182 #interrupt-cells = <1> 145 #interrupt-cells = <1>;
183 compatible = "riscv,cp 146 compatible = "riscv,cpu-intc";
184 interrupt-controller; 147 interrupt-controller;
185 }; 148 };
186 }; 149 };
187 }; 150 };
188 151
189 - | 152 - |
190 // Example 2: Spike ISA Simulator with 1 H 153 // Example 2: Spike ISA Simulator with 1 Hart
191 cpus { 154 cpus {
192 #address-cells = <1>; 155 #address-cells = <1>;
193 #size-cells = <0>; 156 #size-cells = <0>;
194 cpu@0 { 157 cpu@0 {
195 device_type = "cpu"; 158 device_type = "cpu";
196 reg = <0>; 159 reg = <0>;
197 compatible = "riscv"; 160 compatible = "riscv";
>> 161 riscv,isa = "rv64imafdc";
198 mmu-type = "riscv,sv48"; 162 mmu-type = "riscv,sv48";
199 riscv,isa-base = "rv64i"; <<
200 riscv,isa-extensions = "i", "m <<
201 <<
202 interrupt-controller { 163 interrupt-controller {
203 #interrupt-cells = <1> 164 #interrupt-cells = <1>;
204 interrupt-controller; 165 interrupt-controller;
205 compatible = "riscv,cp 166 compatible = "riscv,cpu-intc";
206 }; 167 };
207 }; 168 };
208 }; 169 };
209 ... 170 ...
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