1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/riscv/cpus. 4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: RISC-V CPUs !! 7 title: RISC-V bindings for 'cpus' DT nodes
8 8
9 maintainers: 9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com> 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org> <<
13 12
14 description: | 13 description: |
15 This document uses some terminology common t 14 This document uses some terminology common to the RISC-V community
16 that is not widely used, the definitions of 15 that is not widely used, the definitions of which are listed here:
17 16
18 hart: A hardware execution context, which co 17 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some re 18 mandated by the RISC-V ISA: a PC and some registers. This
20 terminology is designed to disambiguate soft 19 terminology is designed to disambiguate software's view of execution
21 contexts from any particular microarchitectu 20 contexts from any particular microarchitectural implementation
22 strategy. For example, an Intel laptop cont 21 strategy. For example, an Intel laptop containing one socket with
23 two cores, each of which has two hyperthread 22 two cores, each of which has two hyperthreads, could be described as
24 having four harts. 23 having four harts.
25 24
26 allOf: <<
27 - $ref: /schemas/cpu.yaml# <<
28 - $ref: extensions.yaml <<
29 <<
30 properties: 25 properties:
31 compatible: 26 compatible:
32 oneOf: 27 oneOf:
33 - items: 28 - items:
34 - enum: 29 - enum:
35 - amd,mbv32 <<
36 - andestech,ax45mp <<
37 - canaan,k210 <<
38 - sifive,bullet0 <<
39 - sifive,e5 <<
40 - sifive,e7 <<
41 - sifive,e71 <<
42 - sifive,rocket0 30 - sifive,rocket0
43 - sifive,s7 !! 31 - sifive,e5
44 - sifive,u5 <<
45 - sifive,u54 <<
46 - sifive,u7 <<
47 - sifive,u74 <<
48 - sifive,u74-mc <<
49 - thead,c906 <<
50 - thead,c908 <<
51 - thead,c910 <<
52 - thead,c920 <<
53 - const: riscv <<
54 - items: <<
55 - enum: <<
56 - sifive,e51 32 - sifive,e51
57 - sifive,u54-mc 33 - sifive,u54-mc
58 - const: sifive,rocket0 !! 34 - sifive,u54
>> 35 - sifive,u5
59 - const: riscv 36 - const: riscv
60 - const: riscv # Simulator only 37 - const: riscv # Simulator only
61 description: 38 description:
62 Identifies that the hart uses the RISC-V 39 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart. 40 and identifies the type of the hart.
64 41
65 mmu-type: 42 mmu-type:
66 description: 43 description:
67 Identifies the largest MMU address trans !! 44 Identifies the MMU address translation mode used on this
68 this hart. These values originate from !! 45 hart. These values originate from the RISC-V Privileged
69 Specification document, available from 46 Specification document, available from
70 https://riscv.org/specifications/ 47 https://riscv.org/specifications/
71 $ref: /schemas/types.yaml#/definitions/str !! 48 $ref: "/schemas/types.yaml#/definitions/string"
72 enum: 49 enum:
73 - riscv,sv32 50 - riscv,sv32
74 - riscv,sv39 51 - riscv,sv39
75 - riscv,sv48 52 - riscv,sv48
76 - riscv,sv57 <<
77 - riscv,none <<
78 <<
79 reg: <<
80 description: <<
81 The hart ID of this CPU node. <<
82 53
83 riscv,cbom-block-size: !! 54 riscv,isa:
84 $ref: /schemas/types.yaml#/definitions/uin <<
85 description: 55 description:
86 The blocksize in bytes for the Zicbom ca !! 56 Identifies the specific RISC-V instruction set architecture
87 !! 57 supported by the hart. These are documented in the RISC-V
88 riscv,cbop-block-size: !! 58 User-Level ISA document, available from
89 $ref: /schemas/types.yaml#/definitions/uin !! 59 https://riscv.org/specifications/
90 description: <<
91 The blocksize in bytes for the Zicbop ca <<
92 60
93 riscv,cboz-block-size: !! 61 While the isa strings in ISA specification are case
94 $ref: /schemas/types.yaml#/definitions/uin !! 62 insensitive, letters in the riscv,isa string must be all
95 description: !! 63 lowercase to simplify parsing.
96 The blocksize in bytes for the Zicboz ca !! 64 $ref: "/schemas/types.yaml#/definitions/string"
>> 65 enum:
>> 66 - rv64imac
>> 67 - rv64imafdc
97 68
98 # RISC-V has multiple properties for cache o <<
99 # differ between individual CBO extensions <<
100 cache-op-block-size: false <<
101 # RISC-V requires 'timebase-frequency' in /c 69 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
102 timebase-frequency: false 70 timebase-frequency: false
103 71
104 interrupt-controller: 72 interrupt-controller:
105 type: object 73 type: object
106 $ref: /schemas/interrupt-controller/riscv, !! 74 description: Describes the CPU's local interrupt controller
107 75
108 cpu-idle-states: !! 76 properties:
109 $ref: /schemas/types.yaml#/definitions/pha !! 77 '#interrupt-cells':
110 items: !! 78 const: 1
111 maxItems: 1 <<
112 description: | <<
113 List of phandles to idle state nodes sup <<
114 by this hart (see ./idle-states.yaml). <<
115 79
116 capacity-dmips-mhz: !! 80 compatible:
117 description: !! 81 const: riscv,cpu-intc
118 u32 value representing CPU capacity (see !! 82
119 DMIPS/MHz, relative to highest capacity- !! 83 interrupt-controller: true
120 in the system. !! 84
121 !! 85 required:
122 anyOf: !! 86 - '#interrupt-cells'
123 - required: !! 87 - compatible
124 - riscv,isa !! 88 - interrupt-controller
125 - required: <<
126 - riscv,isa-base <<
127 <<
128 dependencies: <<
129 riscv,isa-base: [ "riscv,isa-extensions" ] <<
130 riscv,isa-extensions: [ "riscv,isa-base" ] <<
131 89
132 required: 90 required:
>> 91 - riscv,isa
133 - interrupt-controller 92 - interrupt-controller
134 93
135 unevaluatedProperties: false <<
136 <<
137 examples: 94 examples:
138 - | 95 - |
139 // Example 1: SiFive Freedom U540G Develop 96 // Example 1: SiFive Freedom U540G Development Kit
140 cpus { 97 cpus {
141 #address-cells = <1>; 98 #address-cells = <1>;
142 #size-cells = <0>; 99 #size-cells = <0>;
143 timebase-frequency = <1000000>; 100 timebase-frequency = <1000000>;
144 cpu@0 { 101 cpu@0 {
145 clock-frequency = <0>; 102 clock-frequency = <0>;
146 compatible = "sifive,rocket0", 103 compatible = "sifive,rocket0", "riscv";
147 device_type = "cpu"; 104 device_type = "cpu";
148 i-cache-block-size = <64>; 105 i-cache-block-size = <64>;
149 i-cache-sets = <128>; 106 i-cache-sets = <128>;
150 i-cache-size = <16384>; 107 i-cache-size = <16384>;
151 reg = <0>; 108 reg = <0>;
152 riscv,isa-base = "rv64i"; !! 109 riscv,isa = "rv64imac";
153 riscv,isa-extensions = "i", "m <<
154 <<
155 cpu_intc0: interrupt-controlle 110 cpu_intc0: interrupt-controller {
156 #interrupt-cells = <1> 111 #interrupt-cells = <1>;
157 compatible = "riscv,cp 112 compatible = "riscv,cpu-intc";
158 interrupt-controller; 113 interrupt-controller;
159 }; 114 };
160 }; 115 };
161 cpu@1 { 116 cpu@1 {
162 clock-frequency = <0>; 117 clock-frequency = <0>;
163 compatible = "sifive,rocket0", 118 compatible = "sifive,rocket0", "riscv";
164 d-cache-block-size = <64>; 119 d-cache-block-size = <64>;
165 d-cache-sets = <64>; 120 d-cache-sets = <64>;
166 d-cache-size = <32768>; 121 d-cache-size = <32768>;
167 d-tlb-sets = <1>; 122 d-tlb-sets = <1>;
168 d-tlb-size = <32>; 123 d-tlb-size = <32>;
169 device_type = "cpu"; 124 device_type = "cpu";
170 i-cache-block-size = <64>; 125 i-cache-block-size = <64>;
171 i-cache-sets = <64>; 126 i-cache-sets = <64>;
172 i-cache-size = <32768>; 127 i-cache-size = <32768>;
173 i-tlb-sets = <1>; 128 i-tlb-sets = <1>;
174 i-tlb-size = <32>; 129 i-tlb-size = <32>;
175 mmu-type = "riscv,sv39"; 130 mmu-type = "riscv,sv39";
176 reg = <1>; 131 reg = <1>;
>> 132 riscv,isa = "rv64imafdc";
177 tlb-split; 133 tlb-split;
178 riscv,isa-base = "rv64i"; <<
179 riscv,isa-extensions = "i", "m <<
180 <<
181 cpu_intc1: interrupt-controlle 134 cpu_intc1: interrupt-controller {
182 #interrupt-cells = <1> 135 #interrupt-cells = <1>;
183 compatible = "riscv,cp 136 compatible = "riscv,cpu-intc";
184 interrupt-controller; 137 interrupt-controller;
185 }; 138 };
186 }; 139 };
187 }; 140 };
188 141
189 - | 142 - |
190 // Example 2: Spike ISA Simulator with 1 H 143 // Example 2: Spike ISA Simulator with 1 Hart
191 cpus { 144 cpus {
192 #address-cells = <1>; 145 #address-cells = <1>;
193 #size-cells = <0>; 146 #size-cells = <0>;
194 cpu@0 { 147 cpu@0 {
195 device_type = "cpu"; 148 device_type = "cpu";
196 reg = <0>; 149 reg = <0>;
197 compatible = "riscv"; 150 compatible = "riscv";
>> 151 riscv,isa = "rv64imafdc";
198 mmu-type = "riscv,sv48"; 152 mmu-type = "riscv,sv48";
199 riscv,isa-base = "rv64i"; <<
200 riscv,isa-extensions = "i", "m <<
201 <<
202 interrupt-controller { 153 interrupt-controller {
203 #interrupt-cells = <1> 154 #interrupt-cells = <1>;
204 interrupt-controller; 155 interrupt-controller;
205 compatible = "riscv,cp 156 compatible = "riscv,cpu-intc";
206 }; 157 };
207 }; 158 };
208 }; 159 };
209 ... 160 ...
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