1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/riscv/cpus. 4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: RISC-V CPUs 7 title: RISC-V CPUs
8 8
9 maintainers: 9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com> 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org> 12 - Conor Dooley <conor@kernel.org>
13 13
14 description: | 14 description: |
15 This document uses some terminology common t 15 This document uses some terminology common to the RISC-V community
16 that is not widely used, the definitions of 16 that is not widely used, the definitions of which are listed here:
17 17
18 hart: A hardware execution context, which co 18 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some re 19 mandated by the RISC-V ISA: a PC and some registers. This
20 terminology is designed to disambiguate soft 20 terminology is designed to disambiguate software's view of execution
21 contexts from any particular microarchitectu 21 contexts from any particular microarchitectural implementation
22 strategy. For example, an Intel laptop cont 22 strategy. For example, an Intel laptop containing one socket with
23 two cores, each of which has two hyperthread 23 two cores, each of which has two hyperthreads, could be described as
24 having four harts. 24 having four harts.
25 25
26 allOf: <<
27 - $ref: /schemas/cpu.yaml# <<
28 - $ref: extensions.yaml <<
29 <<
30 properties: 26 properties:
31 compatible: 27 compatible:
32 oneOf: 28 oneOf:
33 - items: 29 - items:
34 - enum: 30 - enum:
35 - amd,mbv32 <<
36 - andestech,ax45mp 31 - andestech,ax45mp
37 - canaan,k210 32 - canaan,k210
38 - sifive,bullet0 33 - sifive,bullet0
39 - sifive,e5 34 - sifive,e5
40 - sifive,e7 35 - sifive,e7
41 - sifive,e71 36 - sifive,e71
42 - sifive,rocket0 37 - sifive,rocket0
43 - sifive,s7 <<
44 - sifive,u5 38 - sifive,u5
45 - sifive,u54 39 - sifive,u54
46 - sifive,u7 40 - sifive,u7
47 - sifive,u74 41 - sifive,u74
48 - sifive,u74-mc 42 - sifive,u74-mc
49 - thead,c906 43 - thead,c906
50 - thead,c908 <<
51 - thead,c910 44 - thead,c910
52 - thead,c920 <<
53 - const: riscv 45 - const: riscv
54 - items: 46 - items:
55 - enum: 47 - enum:
56 - sifive,e51 48 - sifive,e51
57 - sifive,u54-mc 49 - sifive,u54-mc
58 - const: sifive,rocket0 50 - const: sifive,rocket0
59 - const: riscv 51 - const: riscv
60 - const: riscv # Simulator only 52 - const: riscv # Simulator only
61 description: 53 description:
62 Identifies that the hart uses the RISC-V 54 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart. 55 and identifies the type of the hart.
64 56
65 mmu-type: 57 mmu-type:
66 description: 58 description:
67 Identifies the largest MMU address trans !! 59 Identifies the MMU address translation mode used on this
68 this hart. These values originate from !! 60 hart. These values originate from the RISC-V Privileged
69 Specification document, available from 61 Specification document, available from
70 https://riscv.org/specifications/ 62 https://riscv.org/specifications/
71 $ref: /schemas/types.yaml#/definitions/str !! 63 $ref: "/schemas/types.yaml#/definitions/string"
72 enum: 64 enum:
73 - riscv,sv32 65 - riscv,sv32
74 - riscv,sv39 66 - riscv,sv39
75 - riscv,sv48 67 - riscv,sv48
76 - riscv,sv57 <<
77 - riscv,none 68 - riscv,none
78 69
79 reg: <<
80 description: <<
81 The hart ID of this CPU node. <<
82 <<
83 riscv,cbom-block-size: 70 riscv,cbom-block-size:
84 $ref: /schemas/types.yaml#/definitions/uin 71 $ref: /schemas/types.yaml#/definitions/uint32
85 description: 72 description:
86 The blocksize in bytes for the Zicbom ca 73 The blocksize in bytes for the Zicbom cache operations.
87 74
88 riscv,cbop-block-size: !! 75 riscv,isa:
89 $ref: /schemas/types.yaml#/definitions/uin <<
90 description: 76 description:
91 The blocksize in bytes for the Zicbop ca !! 77 Identifies the specific RISC-V instruction set architecture
>> 78 supported by the hart. These are documented in the RISC-V
>> 79 User-Level ISA document, available from
>> 80 https://riscv.org/specifications/
92 81
93 riscv,cboz-block-size: !! 82 While the isa strings in ISA specification are case
94 $ref: /schemas/types.yaml#/definitions/uin !! 83 insensitive, letters in the riscv,isa string must be all
95 description: !! 84 lowercase to simplify parsing.
96 The blocksize in bytes for the Zicboz ca !! 85 $ref: "/schemas/types.yaml#/definitions/string"
>> 86 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
97 87
98 # RISC-V has multiple properties for cache o <<
99 # differ between individual CBO extensions <<
100 cache-op-block-size: false <<
101 # RISC-V requires 'timebase-frequency' in /c 88 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
102 timebase-frequency: false 89 timebase-frequency: false
103 90
104 interrupt-controller: 91 interrupt-controller:
105 type: object 92 type: object
106 $ref: /schemas/interrupt-controller/riscv, !! 93 description: Describes the CPU's local interrupt controller
>> 94
>> 95 properties:
>> 96 '#interrupt-cells':
>> 97 const: 1
>> 98
>> 99 compatible:
>> 100 const: riscv,cpu-intc
>> 101
>> 102 interrupt-controller: true
>> 103
>> 104 required:
>> 105 - '#interrupt-cells'
>> 106 - compatible
>> 107 - interrupt-controller
107 108
108 cpu-idle-states: 109 cpu-idle-states:
109 $ref: /schemas/types.yaml#/definitions/pha !! 110 $ref: '/schemas/types.yaml#/definitions/phandle-array'
110 items: 111 items:
111 maxItems: 1 112 maxItems: 1
112 description: | 113 description: |
113 List of phandles to idle state nodes sup 114 List of phandles to idle state nodes supported
114 by this hart (see ./idle-states.yaml). 115 by this hart (see ./idle-states.yaml).
115 116
116 capacity-dmips-mhz: 117 capacity-dmips-mhz:
117 description: 118 description:
118 u32 value representing CPU capacity (see 119 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
119 DMIPS/MHz, relative to highest capacity- 120 DMIPS/MHz, relative to highest capacity-dmips-mhz
120 in the system. 121 in the system.
121 122
122 anyOf: <<
123 - required: <<
124 - riscv,isa <<
125 - required: <<
126 - riscv,isa-base <<
127 <<
128 dependencies: <<
129 riscv,isa-base: [ "riscv,isa-extensions" ] <<
130 riscv,isa-extensions: [ "riscv,isa-base" ] <<
131 <<
132 required: 123 required:
>> 124 - riscv,isa
133 - interrupt-controller 125 - interrupt-controller
134 126
135 unevaluatedProperties: false !! 127 additionalProperties: true
136 128
137 examples: 129 examples:
138 - | 130 - |
139 // Example 1: SiFive Freedom U540G Develop 131 // Example 1: SiFive Freedom U540G Development Kit
140 cpus { 132 cpus {
141 #address-cells = <1>; 133 #address-cells = <1>;
142 #size-cells = <0>; 134 #size-cells = <0>;
143 timebase-frequency = <1000000>; 135 timebase-frequency = <1000000>;
144 cpu@0 { 136 cpu@0 {
145 clock-frequency = <0>; 137 clock-frequency = <0>;
146 compatible = "sifive,rocket0", 138 compatible = "sifive,rocket0", "riscv";
147 device_type = "cpu"; 139 device_type = "cpu";
148 i-cache-block-size = <64>; 140 i-cache-block-size = <64>;
149 i-cache-sets = <128>; 141 i-cache-sets = <128>;
150 i-cache-size = <16384>; 142 i-cache-size = <16384>;
151 reg = <0>; 143 reg = <0>;
152 riscv,isa-base = "rv64i"; !! 144 riscv,isa = "rv64imac";
153 riscv,isa-extensions = "i", "m <<
154 <<
155 cpu_intc0: interrupt-controlle 145 cpu_intc0: interrupt-controller {
156 #interrupt-cells = <1> 146 #interrupt-cells = <1>;
157 compatible = "riscv,cp 147 compatible = "riscv,cpu-intc";
158 interrupt-controller; 148 interrupt-controller;
159 }; 149 };
160 }; 150 };
161 cpu@1 { 151 cpu@1 {
162 clock-frequency = <0>; 152 clock-frequency = <0>;
163 compatible = "sifive,rocket0", 153 compatible = "sifive,rocket0", "riscv";
164 d-cache-block-size = <64>; 154 d-cache-block-size = <64>;
165 d-cache-sets = <64>; 155 d-cache-sets = <64>;
166 d-cache-size = <32768>; 156 d-cache-size = <32768>;
167 d-tlb-sets = <1>; 157 d-tlb-sets = <1>;
168 d-tlb-size = <32>; 158 d-tlb-size = <32>;
169 device_type = "cpu"; 159 device_type = "cpu";
170 i-cache-block-size = <64>; 160 i-cache-block-size = <64>;
171 i-cache-sets = <64>; 161 i-cache-sets = <64>;
172 i-cache-size = <32768>; 162 i-cache-size = <32768>;
173 i-tlb-sets = <1>; 163 i-tlb-sets = <1>;
174 i-tlb-size = <32>; 164 i-tlb-size = <32>;
175 mmu-type = "riscv,sv39"; 165 mmu-type = "riscv,sv39";
176 reg = <1>; 166 reg = <1>;
>> 167 riscv,isa = "rv64imafdc";
177 tlb-split; 168 tlb-split;
178 riscv,isa-base = "rv64i"; <<
179 riscv,isa-extensions = "i", "m <<
180 <<
181 cpu_intc1: interrupt-controlle 169 cpu_intc1: interrupt-controller {
182 #interrupt-cells = <1> 170 #interrupt-cells = <1>;
183 compatible = "riscv,cp 171 compatible = "riscv,cpu-intc";
184 interrupt-controller; 172 interrupt-controller;
185 }; 173 };
186 }; 174 };
187 }; 175 };
188 176
189 - | 177 - |
190 // Example 2: Spike ISA Simulator with 1 H 178 // Example 2: Spike ISA Simulator with 1 Hart
191 cpus { 179 cpus {
192 #address-cells = <1>; 180 #address-cells = <1>;
193 #size-cells = <0>; 181 #size-cells = <0>;
194 cpu@0 { 182 cpu@0 {
195 device_type = "cpu"; 183 device_type = "cpu";
196 reg = <0>; 184 reg = <0>;
197 compatible = "riscv"; 185 compatible = "riscv";
>> 186 riscv,isa = "rv64imafdc";
198 mmu-type = "riscv,sv48"; 187 mmu-type = "riscv,sv48";
199 riscv,isa-base = "rv64i"; <<
200 riscv,isa-extensions = "i", "m <<
201 <<
202 interrupt-controller { 188 interrupt-controller {
203 #interrupt-cells = <1> 189 #interrupt-cells = <1>;
204 interrupt-controller; 190 interrupt-controller;
205 compatible = "riscv,cp 191 compatible = "riscv,cpu-intc";
206 }; 192 };
207 }; 193 };
208 }; 194 };
209 ... 195 ...
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.