1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/riscv/cpus. 4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: RISC-V CPUs 7 title: RISC-V CPUs
8 8
9 maintainers: 9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com> 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org> 12 - Conor Dooley <conor@kernel.org>
13 13
14 description: | 14 description: |
15 This document uses some terminology common t 15 This document uses some terminology common to the RISC-V community
16 that is not widely used, the definitions of 16 that is not widely used, the definitions of which are listed here:
17 17
18 hart: A hardware execution context, which co 18 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some re 19 mandated by the RISC-V ISA: a PC and some registers. This
20 terminology is designed to disambiguate soft 20 terminology is designed to disambiguate software's view of execution
21 contexts from any particular microarchitectu 21 contexts from any particular microarchitectural implementation
22 strategy. For example, an Intel laptop cont 22 strategy. For example, an Intel laptop containing one socket with
23 two cores, each of which has two hyperthread 23 two cores, each of which has two hyperthreads, could be described as
24 having four harts. 24 having four harts.
25 25
26 allOf: 26 allOf:
27 - $ref: /schemas/cpu.yaml# 27 - $ref: /schemas/cpu.yaml#
28 - $ref: extensions.yaml 28 - $ref: extensions.yaml
29 29
30 properties: 30 properties:
31 compatible: 31 compatible:
32 oneOf: 32 oneOf:
33 - items: 33 - items:
34 - enum: 34 - enum:
35 - amd,mbv32 <<
36 - andestech,ax45mp 35 - andestech,ax45mp
37 - canaan,k210 36 - canaan,k210
38 - sifive,bullet0 37 - sifive,bullet0
39 - sifive,e5 38 - sifive,e5
40 - sifive,e7 39 - sifive,e7
41 - sifive,e71 40 - sifive,e71
42 - sifive,rocket0 41 - sifive,rocket0
43 - sifive,s7 42 - sifive,s7
44 - sifive,u5 43 - sifive,u5
45 - sifive,u54 44 - sifive,u54
46 - sifive,u7 45 - sifive,u7
47 - sifive,u74 46 - sifive,u74
48 - sifive,u74-mc 47 - sifive,u74-mc
49 - thead,c906 48 - thead,c906
50 - thead,c908 <<
51 - thead,c910 49 - thead,c910
52 - thead,c920 50 - thead,c920
53 - const: riscv 51 - const: riscv
54 - items: 52 - items:
55 - enum: 53 - enum:
56 - sifive,e51 54 - sifive,e51
57 - sifive,u54-mc 55 - sifive,u54-mc
58 - const: sifive,rocket0 56 - const: sifive,rocket0
59 - const: riscv 57 - const: riscv
60 - const: riscv # Simulator only 58 - const: riscv # Simulator only
61 description: 59 description:
62 Identifies that the hart uses the RISC-V 60 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart. 61 and identifies the type of the hart.
64 62
65 mmu-type: 63 mmu-type:
66 description: 64 description:
67 Identifies the largest MMU address trans !! 65 Identifies the MMU address translation mode used on this
68 this hart. These values originate from !! 66 hart. These values originate from the RISC-V Privileged
69 Specification document, available from 67 Specification document, available from
70 https://riscv.org/specifications/ 68 https://riscv.org/specifications/
71 $ref: /schemas/types.yaml#/definitions/str 69 $ref: /schemas/types.yaml#/definitions/string
72 enum: 70 enum:
73 - riscv,sv32 71 - riscv,sv32
74 - riscv,sv39 72 - riscv,sv39
75 - riscv,sv48 73 - riscv,sv48
76 - riscv,sv57 74 - riscv,sv57
77 - riscv,none 75 - riscv,none
78 76
79 reg: <<
80 description: <<
81 The hart ID of this CPU node. <<
82 <<
83 riscv,cbom-block-size: 77 riscv,cbom-block-size:
84 $ref: /schemas/types.yaml#/definitions/uin 78 $ref: /schemas/types.yaml#/definitions/uint32
85 description: 79 description:
86 The blocksize in bytes for the Zicbom ca 80 The blocksize in bytes for the Zicbom cache operations.
87 81
88 riscv,cbop-block-size: <<
89 $ref: /schemas/types.yaml#/definitions/uin <<
90 description: <<
91 The blocksize in bytes for the Zicbop ca <<
92 <<
93 riscv,cboz-block-size: 82 riscv,cboz-block-size:
94 $ref: /schemas/types.yaml#/definitions/uin 83 $ref: /schemas/types.yaml#/definitions/uint32
95 description: 84 description:
96 The blocksize in bytes for the Zicboz ca 85 The blocksize in bytes for the Zicboz cache operations.
97 86
98 # RISC-V has multiple properties for cache o 87 # RISC-V has multiple properties for cache op block sizes as the sizes
99 # differ between individual CBO extensions 88 # differ between individual CBO extensions
100 cache-op-block-size: false 89 cache-op-block-size: false
101 # RISC-V requires 'timebase-frequency' in /c 90 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
102 timebase-frequency: false 91 timebase-frequency: false
103 92
104 interrupt-controller: 93 interrupt-controller:
105 type: object 94 type: object
106 $ref: /schemas/interrupt-controller/riscv, !! 95 additionalProperties: false
>> 96 description: Describes the CPU's local interrupt controller
>> 97
>> 98 properties:
>> 99 '#interrupt-cells':
>> 100 const: 1
>> 101
>> 102 compatible:
>> 103 const: riscv,cpu-intc
>> 104
>> 105 interrupt-controller: true
>> 106
>> 107 required:
>> 108 - '#interrupt-cells'
>> 109 - compatible
>> 110 - interrupt-controller
107 111
108 cpu-idle-states: 112 cpu-idle-states:
109 $ref: /schemas/types.yaml#/definitions/pha 113 $ref: /schemas/types.yaml#/definitions/phandle-array
110 items: 114 items:
111 maxItems: 1 115 maxItems: 1
112 description: | 116 description: |
113 List of phandles to idle state nodes sup 117 List of phandles to idle state nodes supported
114 by this hart (see ./idle-states.yaml). 118 by this hart (see ./idle-states.yaml).
115 119
116 capacity-dmips-mhz: 120 capacity-dmips-mhz:
117 description: 121 description:
118 u32 value representing CPU capacity (see 122 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
119 DMIPS/MHz, relative to highest capacity- 123 DMIPS/MHz, relative to highest capacity-dmips-mhz
120 in the system. 124 in the system.
121 125
122 anyOf: 126 anyOf:
123 - required: 127 - required:
124 - riscv,isa 128 - riscv,isa
125 - required: 129 - required:
126 - riscv,isa-base 130 - riscv,isa-base
127 131
128 dependencies: 132 dependencies:
129 riscv,isa-base: [ "riscv,isa-extensions" ] 133 riscv,isa-base: [ "riscv,isa-extensions" ]
130 riscv,isa-extensions: [ "riscv,isa-base" ] 134 riscv,isa-extensions: [ "riscv,isa-base" ]
131 135
132 required: 136 required:
133 - interrupt-controller 137 - interrupt-controller
134 138
135 unevaluatedProperties: false 139 unevaluatedProperties: false
136 140
137 examples: 141 examples:
138 - | 142 - |
139 // Example 1: SiFive Freedom U540G Develop 143 // Example 1: SiFive Freedom U540G Development Kit
140 cpus { 144 cpus {
141 #address-cells = <1>; 145 #address-cells = <1>;
142 #size-cells = <0>; 146 #size-cells = <0>;
143 timebase-frequency = <1000000>; 147 timebase-frequency = <1000000>;
144 cpu@0 { 148 cpu@0 {
145 clock-frequency = <0>; 149 clock-frequency = <0>;
146 compatible = "sifive,rocket0", 150 compatible = "sifive,rocket0", "riscv";
147 device_type = "cpu"; 151 device_type = "cpu";
148 i-cache-block-size = <64>; 152 i-cache-block-size = <64>;
149 i-cache-sets = <128>; 153 i-cache-sets = <128>;
150 i-cache-size = <16384>; 154 i-cache-size = <16384>;
151 reg = <0>; 155 reg = <0>;
152 riscv,isa-base = "rv64i"; 156 riscv,isa-base = "rv64i";
153 riscv,isa-extensions = "i", "m 157 riscv,isa-extensions = "i", "m", "a", "c";
154 158
155 cpu_intc0: interrupt-controlle 159 cpu_intc0: interrupt-controller {
156 #interrupt-cells = <1> 160 #interrupt-cells = <1>;
157 compatible = "riscv,cp 161 compatible = "riscv,cpu-intc";
158 interrupt-controller; 162 interrupt-controller;
159 }; 163 };
160 }; 164 };
161 cpu@1 { 165 cpu@1 {
162 clock-frequency = <0>; 166 clock-frequency = <0>;
163 compatible = "sifive,rocket0", 167 compatible = "sifive,rocket0", "riscv";
164 d-cache-block-size = <64>; 168 d-cache-block-size = <64>;
165 d-cache-sets = <64>; 169 d-cache-sets = <64>;
166 d-cache-size = <32768>; 170 d-cache-size = <32768>;
167 d-tlb-sets = <1>; 171 d-tlb-sets = <1>;
168 d-tlb-size = <32>; 172 d-tlb-size = <32>;
169 device_type = "cpu"; 173 device_type = "cpu";
170 i-cache-block-size = <64>; 174 i-cache-block-size = <64>;
171 i-cache-sets = <64>; 175 i-cache-sets = <64>;
172 i-cache-size = <32768>; 176 i-cache-size = <32768>;
173 i-tlb-sets = <1>; 177 i-tlb-sets = <1>;
174 i-tlb-size = <32>; 178 i-tlb-size = <32>;
175 mmu-type = "riscv,sv39"; 179 mmu-type = "riscv,sv39";
176 reg = <1>; 180 reg = <1>;
177 tlb-split; 181 tlb-split;
178 riscv,isa-base = "rv64i"; 182 riscv,isa-base = "rv64i";
179 riscv,isa-extensions = "i", "m 183 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
180 184
181 cpu_intc1: interrupt-controlle 185 cpu_intc1: interrupt-controller {
182 #interrupt-cells = <1> 186 #interrupt-cells = <1>;
183 compatible = "riscv,cp 187 compatible = "riscv,cpu-intc";
184 interrupt-controller; 188 interrupt-controller;
185 }; 189 };
186 }; 190 };
187 }; 191 };
188 192
189 - | 193 - |
190 // Example 2: Spike ISA Simulator with 1 H 194 // Example 2: Spike ISA Simulator with 1 Hart
191 cpus { 195 cpus {
192 #address-cells = <1>; 196 #address-cells = <1>;
193 #size-cells = <0>; 197 #size-cells = <0>;
194 cpu@0 { 198 cpu@0 {
195 device_type = "cpu"; 199 device_type = "cpu";
196 reg = <0>; 200 reg = <0>;
197 compatible = "riscv"; 201 compatible = "riscv";
198 mmu-type = "riscv,sv48"; 202 mmu-type = "riscv,sv48";
199 riscv,isa-base = "rv64i"; 203 riscv,isa-base = "rv64i";
200 riscv,isa-extensions = "i", "m 204 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
201 205
202 interrupt-controller { 206 interrupt-controller {
203 #interrupt-cells = <1> 207 #interrupt-cells = <1>;
204 interrupt-controller; 208 interrupt-controller;
205 compatible = "riscv,cp 209 compatible = "riscv,cpu-intc";
206 }; 210 };
207 }; 211 };
208 }; 212 };
209 ... 213 ...
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