1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/riscv/cpus. 4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: RISC-V CPUs 7 title: RISC-V CPUs
8 8
9 maintainers: 9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com> 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org> 12 - Conor Dooley <conor@kernel.org>
13 13
14 description: | 14 description: |
15 This document uses some terminology common t 15 This document uses some terminology common to the RISC-V community
16 that is not widely used, the definitions of 16 that is not widely used, the definitions of which are listed here:
17 17
18 hart: A hardware execution context, which co 18 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some re 19 mandated by the RISC-V ISA: a PC and some registers. This
20 terminology is designed to disambiguate soft 20 terminology is designed to disambiguate software's view of execution
21 contexts from any particular microarchitectu 21 contexts from any particular microarchitectural implementation
22 strategy. For example, an Intel laptop cont 22 strategy. For example, an Intel laptop containing one socket with
23 two cores, each of which has two hyperthread 23 two cores, each of which has two hyperthreads, could be described as
24 having four harts. 24 having four harts.
25 25
26 allOf: 26 allOf:
27 - $ref: /schemas/cpu.yaml# 27 - $ref: /schemas/cpu.yaml#
28 - $ref: extensions.yaml 28 - $ref: extensions.yaml
29 29
30 properties: 30 properties:
31 compatible: 31 compatible:
32 oneOf: 32 oneOf:
33 - items: 33 - items:
34 - enum: 34 - enum:
35 - amd,mbv32 35 - amd,mbv32
36 - andestech,ax45mp 36 - andestech,ax45mp
37 - canaan,k210 37 - canaan,k210
38 - sifive,bullet0 38 - sifive,bullet0
39 - sifive,e5 39 - sifive,e5
40 - sifive,e7 40 - sifive,e7
41 - sifive,e71 41 - sifive,e71
42 - sifive,rocket0 42 - sifive,rocket0
43 - sifive,s7 43 - sifive,s7
44 - sifive,u5 44 - sifive,u5
45 - sifive,u54 45 - sifive,u54
46 - sifive,u7 46 - sifive,u7
47 - sifive,u74 47 - sifive,u74
48 - sifive,u74-mc 48 - sifive,u74-mc
49 - thead,c906 49 - thead,c906
50 - thead,c908 <<
51 - thead,c910 50 - thead,c910
52 - thead,c920 51 - thead,c920
53 - const: riscv 52 - const: riscv
54 - items: 53 - items:
55 - enum: 54 - enum:
56 - sifive,e51 55 - sifive,e51
57 - sifive,u54-mc 56 - sifive,u54-mc
58 - const: sifive,rocket0 57 - const: sifive,rocket0
59 - const: riscv 58 - const: riscv
60 - const: riscv # Simulator only 59 - const: riscv # Simulator only
61 description: 60 description:
62 Identifies that the hart uses the RISC-V 61 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart. 62 and identifies the type of the hart.
64 63
65 mmu-type: 64 mmu-type:
66 description: 65 description:
67 Identifies the largest MMU address trans 66 Identifies the largest MMU address translation mode supported by
68 this hart. These values originate from 67 this hart. These values originate from the RISC-V Privileged
69 Specification document, available from 68 Specification document, available from
70 https://riscv.org/specifications/ 69 https://riscv.org/specifications/
71 $ref: /schemas/types.yaml#/definitions/str 70 $ref: /schemas/types.yaml#/definitions/string
72 enum: 71 enum:
73 - riscv,sv32 72 - riscv,sv32
74 - riscv,sv39 73 - riscv,sv39
75 - riscv,sv48 74 - riscv,sv48
76 - riscv,sv57 75 - riscv,sv57
77 - riscv,none 76 - riscv,none
78 77
79 reg: 78 reg:
80 description: 79 description:
81 The hart ID of this CPU node. 80 The hart ID of this CPU node.
82 81
83 riscv,cbom-block-size: 82 riscv,cbom-block-size:
84 $ref: /schemas/types.yaml#/definitions/uin 83 $ref: /schemas/types.yaml#/definitions/uint32
85 description: 84 description:
86 The blocksize in bytes for the Zicbom ca 85 The blocksize in bytes for the Zicbom cache operations.
87 86
88 riscv,cbop-block-size: 87 riscv,cbop-block-size:
89 $ref: /schemas/types.yaml#/definitions/uin 88 $ref: /schemas/types.yaml#/definitions/uint32
90 description: 89 description:
91 The blocksize in bytes for the Zicbop ca 90 The blocksize in bytes for the Zicbop cache operations.
92 91
93 riscv,cboz-block-size: 92 riscv,cboz-block-size:
94 $ref: /schemas/types.yaml#/definitions/uin 93 $ref: /schemas/types.yaml#/definitions/uint32
95 description: 94 description:
96 The blocksize in bytes for the Zicboz ca 95 The blocksize in bytes for the Zicboz cache operations.
97 96
98 # RISC-V has multiple properties for cache o 97 # RISC-V has multiple properties for cache op block sizes as the sizes
99 # differ between individual CBO extensions 98 # differ between individual CBO extensions
100 cache-op-block-size: false 99 cache-op-block-size: false
101 # RISC-V requires 'timebase-frequency' in /c 100 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
102 timebase-frequency: false 101 timebase-frequency: false
103 102
104 interrupt-controller: 103 interrupt-controller:
105 type: object 104 type: object
106 $ref: /schemas/interrupt-controller/riscv, !! 105 additionalProperties: false
>> 106 description: Describes the CPU's local interrupt controller
>> 107
>> 108 properties:
>> 109 '#interrupt-cells':
>> 110 const: 1
>> 111
>> 112 compatible:
>> 113 oneOf:
>> 114 - items:
>> 115 - const: andestech,cpu-intc
>> 116 - const: riscv,cpu-intc
>> 117 - const: riscv,cpu-intc
>> 118
>> 119 interrupt-controller: true
>> 120
>> 121 required:
>> 122 - '#interrupt-cells'
>> 123 - compatible
>> 124 - interrupt-controller
107 125
108 cpu-idle-states: 126 cpu-idle-states:
109 $ref: /schemas/types.yaml#/definitions/pha 127 $ref: /schemas/types.yaml#/definitions/phandle-array
110 items: 128 items:
111 maxItems: 1 129 maxItems: 1
112 description: | 130 description: |
113 List of phandles to idle state nodes sup 131 List of phandles to idle state nodes supported
114 by this hart (see ./idle-states.yaml). 132 by this hart (see ./idle-states.yaml).
115 133
116 capacity-dmips-mhz: 134 capacity-dmips-mhz:
117 description: 135 description:
118 u32 value representing CPU capacity (see 136 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
119 DMIPS/MHz, relative to highest capacity- 137 DMIPS/MHz, relative to highest capacity-dmips-mhz
120 in the system. 138 in the system.
121 139
122 anyOf: 140 anyOf:
123 - required: 141 - required:
124 - riscv,isa 142 - riscv,isa
125 - required: 143 - required:
126 - riscv,isa-base 144 - riscv,isa-base
127 145
128 dependencies: 146 dependencies:
129 riscv,isa-base: [ "riscv,isa-extensions" ] 147 riscv,isa-base: [ "riscv,isa-extensions" ]
130 riscv,isa-extensions: [ "riscv,isa-base" ] 148 riscv,isa-extensions: [ "riscv,isa-base" ]
131 149
132 required: 150 required:
133 - interrupt-controller 151 - interrupt-controller
134 152
135 unevaluatedProperties: false 153 unevaluatedProperties: false
136 154
137 examples: 155 examples:
138 - | 156 - |
139 // Example 1: SiFive Freedom U540G Develop 157 // Example 1: SiFive Freedom U540G Development Kit
140 cpus { 158 cpus {
141 #address-cells = <1>; 159 #address-cells = <1>;
142 #size-cells = <0>; 160 #size-cells = <0>;
143 timebase-frequency = <1000000>; 161 timebase-frequency = <1000000>;
144 cpu@0 { 162 cpu@0 {
145 clock-frequency = <0>; 163 clock-frequency = <0>;
146 compatible = "sifive,rocket0", 164 compatible = "sifive,rocket0", "riscv";
147 device_type = "cpu"; 165 device_type = "cpu";
148 i-cache-block-size = <64>; 166 i-cache-block-size = <64>;
149 i-cache-sets = <128>; 167 i-cache-sets = <128>;
150 i-cache-size = <16384>; 168 i-cache-size = <16384>;
151 reg = <0>; 169 reg = <0>;
152 riscv,isa-base = "rv64i"; 170 riscv,isa-base = "rv64i";
153 riscv,isa-extensions = "i", "m 171 riscv,isa-extensions = "i", "m", "a", "c";
154 172
155 cpu_intc0: interrupt-controlle 173 cpu_intc0: interrupt-controller {
156 #interrupt-cells = <1> 174 #interrupt-cells = <1>;
157 compatible = "riscv,cp 175 compatible = "riscv,cpu-intc";
158 interrupt-controller; 176 interrupt-controller;
159 }; 177 };
160 }; 178 };
161 cpu@1 { 179 cpu@1 {
162 clock-frequency = <0>; 180 clock-frequency = <0>;
163 compatible = "sifive,rocket0", 181 compatible = "sifive,rocket0", "riscv";
164 d-cache-block-size = <64>; 182 d-cache-block-size = <64>;
165 d-cache-sets = <64>; 183 d-cache-sets = <64>;
166 d-cache-size = <32768>; 184 d-cache-size = <32768>;
167 d-tlb-sets = <1>; 185 d-tlb-sets = <1>;
168 d-tlb-size = <32>; 186 d-tlb-size = <32>;
169 device_type = "cpu"; 187 device_type = "cpu";
170 i-cache-block-size = <64>; 188 i-cache-block-size = <64>;
171 i-cache-sets = <64>; 189 i-cache-sets = <64>;
172 i-cache-size = <32768>; 190 i-cache-size = <32768>;
173 i-tlb-sets = <1>; 191 i-tlb-sets = <1>;
174 i-tlb-size = <32>; 192 i-tlb-size = <32>;
175 mmu-type = "riscv,sv39"; 193 mmu-type = "riscv,sv39";
176 reg = <1>; 194 reg = <1>;
177 tlb-split; 195 tlb-split;
178 riscv,isa-base = "rv64i"; 196 riscv,isa-base = "rv64i";
179 riscv,isa-extensions = "i", "m 197 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
180 198
181 cpu_intc1: interrupt-controlle 199 cpu_intc1: interrupt-controller {
182 #interrupt-cells = <1> 200 #interrupt-cells = <1>;
183 compatible = "riscv,cp 201 compatible = "riscv,cpu-intc";
184 interrupt-controller; 202 interrupt-controller;
185 }; 203 };
186 }; 204 };
187 }; 205 };
188 206
189 - | 207 - |
190 // Example 2: Spike ISA Simulator with 1 H 208 // Example 2: Spike ISA Simulator with 1 Hart
191 cpus { 209 cpus {
192 #address-cells = <1>; 210 #address-cells = <1>;
193 #size-cells = <0>; 211 #size-cells = <0>;
194 cpu@0 { 212 cpu@0 {
195 device_type = "cpu"; 213 device_type = "cpu";
196 reg = <0>; 214 reg = <0>;
197 compatible = "riscv"; 215 compatible = "riscv";
198 mmu-type = "riscv,sv48"; 216 mmu-type = "riscv,sv48";
199 riscv,isa-base = "rv64i"; 217 riscv,isa-base = "rv64i";
200 riscv,isa-extensions = "i", "m 218 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
201 219
202 interrupt-controller { 220 interrupt-controller {
203 #interrupt-cells = <1> 221 #interrupt-cells = <1>;
204 interrupt-controller; 222 interrupt-controller;
205 compatible = "riscv,cp 223 compatible = "riscv,cpu-intc";
206 }; 224 };
207 }; 225 };
208 }; 226 };
209 ... 227 ...
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