1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/riscv/exten 4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: RISC-V ISA extensions 7 title: RISC-V ISA extensions
8 8
9 maintainers: 9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com> 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org> 12 - Conor Dooley <conor@kernel.org>
13 13
14 description: | 14 description: |
15 RISC-V has a large number of extensions, som 15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RIS 16 extensions, meaning they are ratified by RISC-V International, and others
17 are "vendor" extensions. 17 are "vendor" extensions.
18 This document defines properties that indica 18 This document defines properties that indicate whether a hart supports a
19 given extension. 19 given extension.
20 20
21 Once a standard extension has been ratified, 21 Once a standard extension has been ratified, no changes in behaviour can be
22 made without the creation of a new extension 22 made without the creation of a new extension.
23 The properties for standard extensions there 23 The properties for standard extensions therefore map to their originally
24 ratified states, with the exception of the I 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions.
25 See the "i" property for more information. 25 See the "i" property for more information.
26 26
27 select: 27 select:
28 properties: 28 properties:
29 compatible: 29 compatible:
30 contains: 30 contains:
31 const: riscv 31 const: riscv
32 32
33 properties: 33 properties:
34 riscv,isa: 34 riscv,isa:
35 description: 35 description:
36 Identifies the specific RISC-V instructi 36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are docume 37 supported by the hart. These are documented in the RISC-V
38 User-Level ISA document, available from 38 User-Level ISA document, available from
39 https://riscv.org/specifications/ 39 https://riscv.org/specifications/
40 40
41 Due to revisions of the ISA specificatio 41 Due to revisions of the ISA specification, some deviations
42 have arisen over time. 42 have arisen over time.
43 Notably, riscv,isa was defined prior to 43 Notably, riscv,isa was defined prior to the creation of the
44 Zicntr, Zicsr, Zifencei and Zihpm extens 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
45 implies "zicntr_zicsr_zifencei_zihpm". 45 implies "zicntr_zicsr_zifencei_zihpm".
46 46
47 While the isa strings in ISA specificati 47 While the isa strings in ISA specification are case
48 insensitive, letters in the riscv,isa st 48 insensitive, letters in the riscv,isa string must be all
49 lowercase. 49 lowercase.
50 $ref: /schemas/types.yaml#/definitions/str 50 $ref: /schemas/types.yaml#/definitions/string
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v? 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
52 deprecated: true 52 deprecated: true
53 53
54 riscv,isa-base: 54 riscv,isa-base:
55 description: 55 description:
56 The base ISA implemented by this hart, a 56 The base ISA implemented by this hart, as described by the 20191213
57 version of the unprivileged ISA specific 57 version of the unprivileged ISA specification.
58 enum: 58 enum:
59 - rv32i 59 - rv32i
60 - rv64i 60 - rv64i
61 61
62 riscv,isa-extensions: 62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/str 63 $ref: /schemas/types.yaml#/definitions/string-array
64 minItems: 1 64 minItems: 1
65 description: Extensions supported by the h 65 description: Extensions supported by the hart.
66 items: 66 items:
67 anyOf: 67 anyOf:
68 # single letter extensions, in canonic 68 # single letter extensions, in canonical order
69 - const: i 69 - const: i
70 description: | 70 description: |
71 The base integer instruction set, 71 The base integer instruction set, as ratified in the 20191213
72 version of the unprivileged ISA sp 72 version of the unprivileged ISA specification.
73 73
74 This does not include Chapter 10, 74 This does not include Chapter 10, "Counters", which was moved into
75 the Zicntr and Zihpm extensions af 75 the Zicntr and Zihpm extensions after the ratification of the
76 20191213 version of the unprivileg 76 20191213 version of the unprivileged specification.
77 77
78 - const: m 78 - const: m
79 description: 79 description:
80 The standard M extension for integ 80 The standard M extension for integer multiplication and division, as
81 ratified in the 20191213 version o 81 ratified in the 20191213 version of the unprivileged ISA
82 specification. 82 specification.
83 83
84 - const: a 84 - const: a
85 description: 85 description:
86 The standard A extension for atomi 86 The standard A extension for atomic instructions, as ratified in the
87 20191213 version of the unprivileg 87 20191213 version of the unprivileged ISA specification.
88 88
89 - const: f 89 - const: f
90 description: 90 description:
91 The standard F extension for singl 91 The standard F extension for single-precision floating point, as
92 ratified in the 20191213 version o 92 ratified in the 20191213 version of the unprivileged ISA
93 specification. 93 specification.
94 94
95 - const: d 95 - const: d
96 description: 96 description:
97 The standard D extension for doubl 97 The standard D extension for double-precision floating-point, as
98 ratified in the 20191213 version o 98 ratified in the 20191213 version of the unprivileged ISA
99 specification. 99 specification.
100 100
101 - const: q 101 - const: q
102 description: 102 description:
103 The standard Q extension for quad- 103 The standard Q extension for quad-precision floating-point, as
104 ratified in the 20191213 version o 104 ratified in the 20191213 version of the unprivileged ISA
105 specification. 105 specification.
106 106
107 - const: c 107 - const: c
108 description: 108 description:
109 The standard C extension for compr 109 The standard C extension for compressed instructions, as ratified in
110 the 20191213 version of the unpriv 110 the 20191213 version of the unprivileged ISA specification.
111 111
112 - const: v 112 - const: v
113 description: 113 description:
114 The standard V extension for vecto 114 The standard V extension for vector operations, as ratified
115 in-and-around commit 7a6c8ae ("Fix 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116 encoding") of the riscv-v-spec. 116 encoding") of the riscv-v-spec.
117 117
118 - const: h 118 - const: h
119 description: 119 description:
120 The standard H extension for hyper 120 The standard H extension for hypervisors as ratified in the 20191213
121 version of the privileged ISA spec 121 version of the privileged ISA specification.
122 122
123 # multi-letter extensions, sorted alph 123 # multi-letter extensions, sorted alphanumerically
124 - const: smaia 124 - const: smaia
125 description: | 125 description: |
126 The standard Smaia supervisor-leve 126 The standard Smaia supervisor-level extension for the advanced
127 interrupt architecture for machine 127 interrupt architecture for machine-mode-visible csr and behavioural
128 changes to interrupts as frozen at 128 changes to interrupts as frozen at commit ccbddab ("Merge pull
129 request #42 from riscv/jhauser-202 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
130 130
131 - const: smstateen 131 - const: smstateen
132 description: | 132 description: |
133 The standard Smstateen extension f 133 The standard Smstateen extension for controlling access to CSRs
134 added by other RISC-V extensions i 134 added by other RISC-V extensions in H/S/VS/U/VU modes and as
135 ratified at commit a28bfae (Ratifi 135 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
136 136
137 - const: ssaia 137 - const: ssaia
138 description: | 138 description: |
139 The standard Ssaia supervisor-leve 139 The standard Ssaia supervisor-level extension for the advanced
140 interrupt architecture for supervi 140 interrupt architecture for supervisor-mode-visible csr and
141 behavioural changes to interrupts 141 behavioural changes to interrupts as frozen at commit ccbddab
142 ("Merge pull request #42 from risc 142 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
143 143
144 - const: sscofpmf 144 - const: sscofpmf
145 description: | 145 description: |
146 The standard Sscofpmf supervisor-l 146 The standard Sscofpmf supervisor-level extension for count overflow
147 and mode-based filtering as ratifi 147 and mode-based filtering as ratified at commit 01d1df0 ("Add ability
148 to manually trigger workflow. (#2) 148 to manually trigger workflow. (#2)") of riscv-count-overflow.
149 149
150 - const: sstc 150 - const: sstc
151 description: | 151 description: |
152 The standard Sstc supervisor-level 152 The standard Sstc supervisor-level extension for time compare as
153 ratified at commit 3f9ed34 ("Add a 153 ratified at commit 3f9ed34 ("Add ability to manually trigger
154 workflow. (#2)") of riscv-time-com 154 workflow. (#2)") of riscv-time-compare.
155 155
156 - const: svinval 156 - const: svinval
157 description: 157 description:
158 The standard Svinval supervisor-le 158 The standard Svinval supervisor-level extension for fine-grained
159 address-translation cache invalida 159 address-translation cache invalidation as ratified in the 20191213
160 version of the privileged ISA spec 160 version of the privileged ISA specification.
161 161
162 - const: svnapot 162 - const: svnapot
163 description: 163 description:
164 The standard Svnapot supervisor-le 164 The standard Svnapot supervisor-level extensions for napot
165 translation contiguity as ratified 165 translation contiguity as ratified in the 20191213 version of the
166 privileged ISA specification. 166 privileged ISA specification.
167 167
168 - const: svpbmt 168 - const: svpbmt
169 description: 169 description:
170 The standard Svpbmt supervisor-lev 170 The standard Svpbmt supervisor-level extensions for page-based
171 memory types as ratified in the 20 171 memory types as ratified in the 20191213 version of the privileged
172 ISA specification. 172 ISA specification.
173 173
174 - const: svvptc 174 - const: svvptc
175 description: 175 description:
176 The standard Svvptc supervisor-lev 176 The standard Svvptc supervisor-level extension for
177 address-translation cache behaviou 177 address-translation cache behaviour with respect to invalid entries
178 as ratified at commit 4a69197e5617 178 as ratified at commit 4a69197e5617 ("Update to ratified state") of
179 riscv-svvptc. 179 riscv-svvptc.
180 180
181 - const: zacas 181 - const: zacas
182 description: | 182 description: |
183 The Zacas extension for Atomic Com 183 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
184 is supported as ratified at commit 184 is supported as ratified at commit 5059e0ca641c ("update to
185 ratified") of the riscv-zacas. 185 ratified") of the riscv-zacas.
186 186
187 - const: zawrs 187 - const: zawrs
188 description: | 188 description: |
189 The Zawrs extension for entering a 189 The Zawrs extension for entering a low-power state or for trapping
190 to a hypervisor while waiting on a 190 to a hypervisor while waiting on a store to a memory location, as
191 ratified in commit 98918c844281 (" 191 ratified in commit 98918c844281 ("Merge pull request #1217 from
192 riscv/zawrs") of riscv-isa-manual. 192 riscv/zawrs") of riscv-isa-manual.
193 193
194 - const: zba 194 - const: zba
195 description: | 195 description: |
196 The standard Zba bit-manipulation 196 The standard Zba bit-manipulation extension for address generation
197 acceleration instructions as ratif 197 acceleration instructions as ratified at commit 6d33919 ("Merge pull
198 request #158 from hirooih/clmul-fi 198 request #158 from hirooih/clmul-fix-loop-end-condition") of
199 riscv-bitmanip. 199 riscv-bitmanip.
200 200
201 - const: zbb 201 - const: zbb
202 description: | 202 description: |
203 The standard Zbb bit-manipulation 203 The standard Zbb bit-manipulation extension for basic bit-manipulation
204 as ratified at commit 6d33919 ("Me 204 as ratified at commit 6d33919 ("Merge pull request #158 from
205 hirooih/clmul-fix-loop-end-conditi 205 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
206 206
207 - const: zbc 207 - const: zbc
208 description: | 208 description: |
209 The standard Zbc bit-manipulation 209 The standard Zbc bit-manipulation extension for carry-less
210 multiplication as ratified at comm 210 multiplication as ratified at commit 6d33919 ("Merge pull request
211 #158 from hirooih/clmul-fix-loop-e 211 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
212 212
213 - const: zbkb 213 - const: zbkb
214 description: 214 description:
215 The standard Zbkb bitmanip instruc 215 The standard Zbkb bitmanip instructions for cryptography as ratified
216 in version 1.0 of RISC-V Cryptogra 216 in version 1.0 of RISC-V Cryptography Extensions Volume I
217 specification. 217 specification.
218 218
219 - const: zbkc 219 - const: zbkc
220 description: 220 description:
221 The standard Zbkc carry-less multi 221 The standard Zbkc carry-less multiply instructions as ratified
222 in version 1.0 of RISC-V Cryptogra 222 in version 1.0 of RISC-V Cryptography Extensions Volume I
223 specification. 223 specification.
224 224
225 - const: zbkx 225 - const: zbkx
226 description: 226 description:
227 The standard Zbkx crossbar permuta 227 The standard Zbkx crossbar permutation instructions as ratified
228 in version 1.0 of RISC-V Cryptogra 228 in version 1.0 of RISC-V Cryptography Extensions Volume I
229 specification. 229 specification.
230 230
231 - const: zbs 231 - const: zbs
232 description: | 232 description: |
233 The standard Zbs bit-manipulation 233 The standard Zbs bit-manipulation extension for single-bit
234 instructions as ratified at commit 234 instructions as ratified at commit 6d33919 ("Merge pull request #158
235 from hirooih/clmul-fix-loop-end-co 235 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
236 236
237 - const: zca 237 - const: zca
238 description: | 238 description: |
239 The Zca extension part of Zc* stan 239 The Zca extension part of Zc* standard extensions for code size
240 reduction, as ratified in commit 8 240 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
241 RV64 as it contains no instruction 241 RV64 as it contains no instructions") of riscv-code-size-reduction,
242 merged in the riscv-isa-manual by 242 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
243 of zc.adoc to src tree."). 243 of zc.adoc to src tree.").
244 244
245 - const: zcb 245 - const: zcb
246 description: | 246 description: |
247 The Zcb extension part of Zc* stan 247 The Zcb extension part of Zc* standard extensions for code size
248 reduction, as ratified in commit 8 248 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
249 RV64 as it contains no instruction 249 RV64 as it contains no instructions") of riscv-code-size-reduction,
250 merged in the riscv-isa-manual by 250 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
251 of zc.adoc to src tree."). 251 of zc.adoc to src tree.").
252 252
253 - const: zcd 253 - const: zcd
254 description: | 254 description: |
255 The Zcd extension part of Zc* stan 255 The Zcd extension part of Zc* standard extensions for code size
256 reduction, as ratified in commit 8 256 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
257 RV64 as it contains no instruction 257 RV64 as it contains no instructions") of riscv-code-size-reduction,
258 merged in the riscv-isa-manual by 258 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
259 of zc.adoc to src tree."). 259 of zc.adoc to src tree.").
260 260
261 - const: zcf 261 - const: zcf
262 description: | 262 description: |
263 The Zcf extension part of Zc* stan 263 The Zcf extension part of Zc* standard extensions for code size
264 reduction, as ratified in commit 8 264 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
265 RV64 as it contains no instruction 265 RV64 as it contains no instructions") of riscv-code-size-reduction,
266 merged in the riscv-isa-manual by 266 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
267 of zc.adoc to src tree."). 267 of zc.adoc to src tree.").
268 268
269 - const: zcmop 269 - const: zcmop
270 description: 270 description:
271 The standard Zcmop extension versi 271 The standard Zcmop extension version 1.0, as ratified in commit
272 c732a4f39a4 ("Zcmop is ratified/1. 272 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
273 273
274 - const: zfa 274 - const: zfa
275 description: 275 description:
276 The standard Zfa extension for add 276 The standard Zfa extension for additional floating point
277 instructions, as ratified in commi 277 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
278 riscv-isa-manual. 278 riscv-isa-manual.
279 279
280 - const: zfh 280 - const: zfh
281 description: 281 description:
282 The standard Zfh extension for 16- 282 The standard Zfh extension for 16-bit half-precision binary
283 floating-point instructions, as ra 283 floating-point instructions, as ratified in commit 64074bc ("Update
284 version numbers for Zfh/Zfinx") of 284 version numbers for Zfh/Zfinx") of riscv-isa-manual.
285 285
286 - const: zfhmin 286 - const: zfhmin
287 description: 287 description:
288 The standard Zfhmin extension whic 288 The standard Zfhmin extension which provides minimal support for
289 16-bit half-precision binary float 289 16-bit half-precision binary floating-point instructions, as ratified
290 in commit 64074bc ("Update version 290 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
291 riscv-isa-manual. 291 riscv-isa-manual.
292 292
293 - const: zk 293 - const: zk
294 description: 294 description:
295 The standard Zk Standard Scalar cr 295 The standard Zk Standard Scalar cryptography extension as ratified
296 in version 1.0 of RISC-V Cryptogra 296 in version 1.0 of RISC-V Cryptography Extensions Volume I
297 specification. 297 specification.
298 298
299 - const: zkn 299 - const: zkn
300 description: 300 description:
301 The standard Zkn NIST algorithm su 301 The standard Zkn NIST algorithm suite extensions as ratified in
302 version 1.0 of RISC-V Cryptography 302 version 1.0 of RISC-V Cryptography Extensions Volume I
303 specification. 303 specification.
304 304
305 - const: zknd 305 - const: zknd
306 description: | 306 description: |
307 The standard Zknd for NIST suite: 307 The standard Zknd for NIST suite: AES decryption instructions as
308 ratified in version 1.0 of RISC-V 308 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
309 specification. 309 specification.
310 310
311 - const: zkne 311 - const: zkne
312 description: | 312 description: |
313 The standard Zkne for NIST suite: 313 The standard Zkne for NIST suite: AES encryption instructions as
314 ratified in version 1.0 of RISC-V 314 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
315 specification. 315 specification.
316 316
317 - const: zknh 317 - const: zknh
318 description: | 318 description: |
319 The standard Zknh for NIST suite: 319 The standard Zknh for NIST suite: hash function instructions as
320 ratified in version 1.0 of RISC-V 320 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
321 specification. 321 specification.
322 322
323 - const: zkr 323 - const: zkr
324 description: 324 description:
325 The standard Zkr entropy source ex 325 The standard Zkr entropy source extension as ratified in version
326 1.0 of RISC-V Cryptography Extensi 326 1.0 of RISC-V Cryptography Extensions Volume I specification.
327 This string being present means th 327 This string being present means that the CSR associated to this
328 extension is accessible at the pri 328 extension is accessible at the privilege level to which that
329 device-tree has been provided. 329 device-tree has been provided.
330 330
331 - const: zks 331 - const: zks
332 description: 332 description:
333 The standard Zks ShangMi algorithm 333 The standard Zks ShangMi algorithm suite extensions as ratified in
334 version 1.0 of RISC-V Cryptography 334 version 1.0 of RISC-V Cryptography Extensions Volume I
335 specification. 335 specification.
336 336
337 - const: zksed 337 - const: zksed
338 description: | 338 description: |
339 The standard Zksed for ShangMi sui 339 The standard Zksed for ShangMi suite: SM4 block cipher instructions
340 as ratified in version 1.0 of RISC 340 as ratified in version 1.0 of RISC-V Cryptography Extensions
341 Volume I specification. 341 Volume I specification.
342 342
343 - const: zksh 343 - const: zksh
344 description: | 344 description: |
345 The standard Zksh for ShangMi suit 345 The standard Zksh for ShangMi suite: SM3 hash function instructions
346 as ratified in version 1.0 of RISC 346 as ratified in version 1.0 of RISC-V Cryptography Extensions
347 Volume I specification. 347 Volume I specification.
348 348
349 - const: zkt 349 - const: zkt
350 description: 350 description:
351 The standard Zkt for data independ 351 The standard Zkt for data independent execution latency as ratified
352 in version 1.0 of RISC-V Cryptogra 352 in version 1.0 of RISC-V Cryptography Extensions Volume I
353 specification. 353 specification.
354 354
355 - const: zicbom 355 - const: zicbom
356 description: 356 description:
357 The standard Zicbom extension for 357 The standard Zicbom extension for base cache management operations as
358 ratified in commit 3dd606f ("Creat 358 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
359 359
360 - const: zicbop 360 - const: zicbop
361 description: 361 description:
362 The standard Zicbop extension for 362 The standard Zicbop extension for cache-block prefetch instructions
363 as ratified in commit 3dd606f ("Cr 363 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
364 riscv-CMOs. 364 riscv-CMOs.
365 365
366 - const: zicboz 366 - const: zicboz
367 description: 367 description:
368 The standard Zicboz extension for 368 The standard Zicboz extension for cache-block zeroing as ratified
369 in commit 3dd606f ("Create cmobase 369 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
370 370
371 - const: zicntr 371 - const: zicntr
372 description: 372 description:
373 The standard Zicntr extension for 373 The standard Zicntr extension for base counters and timers, as
374 ratified in the 20191213 version o 374 ratified in the 20191213 version of the unprivileged ISA
375 specification. 375 specification.
376 376
377 - const: zicond 377 - const: zicond
378 description: 378 description:
379 The standard Zicond extension for 379 The standard Zicond extension for conditional arithmetic and
380 conditional-select/move operations 380 conditional-select/move operations as ratified in commit 95cf1f9
381 ("Add changes requested by Ved dur 381 ("Add changes requested by Ved during signoff") of riscv-zicond.
382 382
383 - const: zicsr 383 - const: zicsr
384 description: | 384 description: |
385 The standard Zicsr extension for c 385 The standard Zicsr extension for control and status register
386 instructions, as ratified in the 2 386 instructions, as ratified in the 20191213 version of the
387 unprivileged ISA specification. 387 unprivileged ISA specification.
388 388
389 This does not include Chapter 10, 389 This does not include Chapter 10, "Counters", which documents
390 special case read-only CSRs, that 390 special case read-only CSRs, that were moved into the Zicntr and
391 Zihpm extensions after the ratific 391 Zihpm extensions after the ratification of the 20191213 version of
392 the unprivileged specification. 392 the unprivileged specification.
393 393
394 - const: zifencei 394 - const: zifencei
395 description: 395 description:
396 The standard Zifencei extension fo 396 The standard Zifencei extension for instruction-fetch fence, as
397 ratified in the 20191213 version o 397 ratified in the 20191213 version of the unprivileged ISA
398 specification. 398 specification.
399 399
400 - const: zihintpause 400 - const: zihintpause
401 description: 401 description:
402 The standard Zihintpause extension 402 The standard Zihintpause extension for pause hints, as ratified in
403 commit d8ab5c7 ("Zihintpause is ra 403 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
404 404
405 - const: zihintntl 405 - const: zihintntl
406 description: 406 description:
407 The standard Zihintntl extension f 407 The standard Zihintntl extension for non-temporal locality hints, as
408 ratified in commit 0dc91f5 ("Zihin 408 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
409 riscv-isa-manual. 409 riscv-isa-manual.
410 410
411 - const: zihpm 411 - const: zihpm
412 description: 412 description:
413 The standard Zihpm extension for h 413 The standard Zihpm extension for hardware performance counters, as
414 ratified in the 20191213 version o 414 ratified in the 20191213 version of the unprivileged ISA
415 specification. 415 specification.
416 416
417 - const: zimop 417 - const: zimop
418 description: 418 description:
419 The standard Zimop extension versi 419 The standard Zimop extension version 1.0, as ratified in commit
420 58220614a5f ("Zimop is ratified/1. 420 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
421 421
422 - const: ztso 422 - const: ztso
423 description: 423 description:
424 The standard Ztso extension for to 424 The standard Ztso extension for total store ordering, as ratified
425 in commit 2e5236 ("Ztso is now rat 425 in commit 2e5236 ("Ztso is now ratified.") of the
426 riscv-isa-manual. 426 riscv-isa-manual.
427 427
428 - const: zvbb 428 - const: zvbb
429 description: 429 description:
430 The standard Zvbb extension for ve 430 The standard Zvbb extension for vectored basic bit-manipulation
431 instructions, as ratified in commi 431 instructions, as ratified in commit 56ed795 ("Update
432 riscv-crypto-spec-vector.adoc") of 432 riscv-crypto-spec-vector.adoc") of riscv-crypto.
433 433
434 - const: zvbc 434 - const: zvbc
435 description: 435 description:
436 The standard Zvbc extension for ve 436 The standard Zvbc extension for vectored carryless multiplication
437 instructions, as ratified in commi 437 instructions, as ratified in commit 56ed795 ("Update
438 riscv-crypto-spec-vector.adoc") of 438 riscv-crypto-spec-vector.adoc") of riscv-crypto.
439 439
440 - const: zve32f 440 - const: zve32f
441 description: 441 description:
442 The standard Zve32f extension for 442 The standard Zve32f extension for embedded processors, as ratified
443 in commit 6f702a2 ("Vector extensi 443 in commit 6f702a2 ("Vector extensions are now ratified") of
444 riscv-v-spec. 444 riscv-v-spec.
445 445
446 - const: zve32x 446 - const: zve32x
447 description: 447 description:
448 The standard Zve32x extension for 448 The standard Zve32x extension for embedded processors, as ratified
449 in commit 6f702a2 ("Vector extensi 449 in commit 6f702a2 ("Vector extensions are now ratified") of
450 riscv-v-spec. 450 riscv-v-spec.
451 451
452 - const: zve64d 452 - const: zve64d
453 description: 453 description:
454 The standard Zve64d extension for 454 The standard Zve64d extension for embedded processors, as ratified
455 in commit 6f702a2 ("Vector extensi 455 in commit 6f702a2 ("Vector extensions are now ratified") of
456 riscv-v-spec. 456 riscv-v-spec.
457 457
458 - const: zve64f 458 - const: zve64f
459 description: 459 description:
460 The standard Zve64f extension for 460 The standard Zve64f extension for embedded processors, as ratified
461 in commit 6f702a2 ("Vector extensi 461 in commit 6f702a2 ("Vector extensions are now ratified") of
462 riscv-v-spec. 462 riscv-v-spec.
463 463
464 - const: zve64x 464 - const: zve64x
465 description: 465 description:
466 The standard Zve64x extension for 466 The standard Zve64x extension for embedded processors, as ratified
467 in commit 6f702a2 ("Vector extensi 467 in commit 6f702a2 ("Vector extensions are now ratified") of
468 riscv-v-spec. 468 riscv-v-spec.
469 469
470 - const: zvfh 470 - const: zvfh
471 description: 471 description:
472 The standard Zvfh extension for ve 472 The standard Zvfh extension for vectored half-precision
473 floating-point instructions, as ra 473 floating-point instructions, as ratified in commit e2ccd05
474 ("Remove draft warnings from Zvfh[ 474 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
475 475
476 - const: zvfhmin 476 - const: zvfhmin
477 description: 477 description:
478 The standard Zvfhmin extension for 478 The standard Zvfhmin extension for vectored minimal half-precision
479 floating-point instructions, as ra 479 floating-point instructions, as ratified in commit e2ccd05
480 ("Remove draft warnings from Zvfh[ 480 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
481 481
482 - const: zvkb 482 - const: zvkb
483 description: 483 description:
484 The standard Zvkb extension for ve 484 The standard Zvkb extension for vector cryptography bit-manipulation
485 instructions, as ratified in commi 485 instructions, as ratified in commit 56ed795 ("Update
486 riscv-crypto-spec-vector.adoc") of 486 riscv-crypto-spec-vector.adoc") of riscv-crypto.
487 487
488 - const: zvkg 488 - const: zvkg
489 description: 489 description:
490 The standard Zvkg extension for ve 490 The standard Zvkg extension for vector GCM/GMAC instructions, as
491 ratified in commit 56ed795 ("Updat 491 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
492 of riscv-crypto. 492 of riscv-crypto.
493 493
494 - const: zvkn 494 - const: zvkn
495 description: 495 description:
496 The standard Zvkn extension for NI 496 The standard Zvkn extension for NIST algorithm suite instructions, as
497 ratified in commit 56ed795 ("Updat 497 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
498 of riscv-crypto. 498 of riscv-crypto.
499 499
500 - const: zvknc 500 - const: zvknc
501 description: 501 description:
502 The standard Zvknc extension for N 502 The standard Zvknc extension for NIST algorithm suite with carryless
503 multiply instructions, as ratified 503 multiply instructions, as ratified in commit 56ed795 ("Update
504 riscv-crypto-spec-vector.adoc") of 504 riscv-crypto-spec-vector.adoc") of riscv-crypto.
505 505
506 - const: zvkned 506 - const: zvkned
507 description: 507 description:
508 The standard Zvkned extension for 508 The standard Zvkned extension for Vector AES block cipher
509 instructions, as ratified in commi 509 instructions, as ratified in commit 56ed795 ("Update
510 riscv-crypto-spec-vector.adoc") of 510 riscv-crypto-spec-vector.adoc") of riscv-crypto.
511 511
512 - const: zvkng 512 - const: zvkng
513 description: 513 description:
514 The standard Zvkng extension for N 514 The standard Zvkng extension for NIST algorithm suite with GCM
515 instructions, as ratified in commi 515 instructions, as ratified in commit 56ed795 ("Update
516 riscv-crypto-spec-vector.adoc") of 516 riscv-crypto-spec-vector.adoc") of riscv-crypto.
517 517
518 - const: zvknha 518 - const: zvknha
519 description: | 519 description: |
520 The standard Zvknha extension for 520 The standard Zvknha extension for NIST suite: vector SHA-2 secure,
521 hash (SHA-256 only) instructions, 521 hash (SHA-256 only) instructions, as ratified in commit
522 56ed795 ("Update riscv-crypto-spec 522 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
523 523
524 - const: zvknhb 524 - const: zvknhb
525 description: | 525 description: |
526 The standard Zvknhb extension for 526 The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
527 hash (SHA-256 and SHA-512) instruc 527 hash (SHA-256 and SHA-512) instructions, as ratified in commit
528 56ed795 ("Update riscv-crypto-spec 528 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
529 529
530 - const: zvks 530 - const: zvks
531 description: 531 description:
532 The standard Zvks extension for Sh 532 The standard Zvks extension for ShangMi algorithm suite
533 instructions, as ratified in commi 533 instructions, as ratified in commit 56ed795 ("Update
534 riscv-crypto-spec-vector.adoc") of 534 riscv-crypto-spec-vector.adoc") of riscv-crypto.
535 535
536 - const: zvksc 536 - const: zvksc
537 description: 537 description:
538 The standard Zvksc extension for S 538 The standard Zvksc extension for ShangMi algorithm suite with
539 carryless multiplication instructi 539 carryless multiplication instructions, as ratified in commit 56ed795
540 ("Update riscv-crypto-spec-vector. 540 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
541 541
542 - const: zvksed 542 - const: zvksed
543 description: | 543 description: |
544 The standard Zvksed extension for 544 The standard Zvksed extension for ShangMi suite: SM4 block cipher
545 instructions, as ratified in commi 545 instructions, as ratified in commit 56ed795 ("Update
546 riscv-crypto-spec-vector.adoc") of 546 riscv-crypto-spec-vector.adoc") of riscv-crypto.
547 547
548 - const: zvksh 548 - const: zvksh
549 description: | 549 description: |
550 The standard Zvksh extension for S 550 The standard Zvksh extension for ShangMi suite: SM3 secure hash
551 instructions, as ratified in commi 551 instructions, as ratified in commit 56ed795 ("Update
552 riscv-crypto-spec-vector.adoc") of 552 riscv-crypto-spec-vector.adoc") of riscv-crypto.
553 553
554 - const: zvksg 554 - const: zvksg
555 description: 555 description:
556 The standard Zvksg extension for S 556 The standard Zvksg extension for ShangMi algorithm suite with GCM
557 instructions, as ratified in commi 557 instructions, as ratified in commit 56ed795 ("Update
558 riscv-crypto-spec-vector.adoc") of 558 riscv-crypto-spec-vector.adoc") of riscv-crypto.
559 559
560 - const: zvkt 560 - const: zvkt
561 description: 561 description:
562 The standard Zvkt extension for ve 562 The standard Zvkt extension for vector data-independent execution
563 latency, as ratified in commit 56e 563 latency, as ratified in commit 56ed795 ("Update
564 riscv-crypto-spec-vector.adoc") of 564 riscv-crypto-spec-vector.adoc") of riscv-crypto.
565 565
566 - const: xandespmu 566 - const: xandespmu
567 description: 567 description:
568 The Andes Technology performance m 568 The Andes Technology performance monitor extension for counter overflow
569 and privilege mode filtering. For 569 and privilege mode filtering. For more details, see Counter Related
570 Registers in the AX45MP datasheet. 570 Registers in the AX45MP datasheet.
571 https://www.andestech.com/wp-conte 571 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
572 572
573 allOf: 573 allOf:
574 # Zcb depends on Zca 574 # Zcb depends on Zca
575 - if: 575 - if:
576 contains: 576 contains:
577 const: zcb 577 const: zcb
578 then: 578 then:
579 contains: 579 contains:
580 const: zca 580 const: zca
581 # Zcd depends on Zca and D 581 # Zcd depends on Zca and D
582 - if: 582 - if:
583 contains: 583 contains:
584 const: zcd 584 const: zcd
585 then: 585 then:
586 allOf: 586 allOf:
587 - contains: 587 - contains:
588 const: zca 588 const: zca
589 - contains: 589 - contains:
590 const: d 590 const: d
591 # Zcf depends on Zca and F 591 # Zcf depends on Zca and F
592 - if: 592 - if:
593 contains: 593 contains:
594 const: zcf 594 const: zcf
595 then: 595 then:
596 allOf: 596 allOf:
597 - contains: 597 - contains:
598 const: zca 598 const: zca
599 - contains: 599 - contains:
600 const: f 600 const: f
601 # Zcmop depends on Zca 601 # Zcmop depends on Zca
602 - if: 602 - if:
603 contains: 603 contains:
604 const: zcmop 604 const: zcmop
605 then: 605 then:
606 contains: 606 contains:
607 const: zca 607 const: zca
608 608
609 allOf: 609 allOf:
610 # Zcf extension does not exist on rv64 610 # Zcf extension does not exist on rv64
611 - if: 611 - if:
612 properties: 612 properties:
613 riscv,isa-extensions: 613 riscv,isa-extensions:
614 contains: 614 contains:
615 const: zcf 615 const: zcf
616 riscv,isa-base: 616 riscv,isa-base:
617 contains: 617 contains:
618 const: rv64i 618 const: rv64i
619 then: 619 then:
620 properties: 620 properties:
621 riscv,isa-extensions: 621 riscv,isa-extensions:
622 not: 622 not:
623 contains: 623 contains:
624 const: zcf 624 const: zcf
625 625
626 additionalProperties: true 626 additionalProperties: true
627 ... 627 ...
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