1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/riscv/exten
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: RISC-V ISA extensions
8
9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
13
14 description: |
15 RISC-V has a large number of extensions, som
16 extensions, meaning they are ratified by RIS
17 are "vendor" extensions.
18 This document defines properties that indica
19 given extension.
20
21 Once a standard extension has been ratified,
22 made without the creation of a new extension
23 The properties for standard extensions there
24 ratified states, with the exception of the I
25 See the "i" property for more information.
26
27 select:
28 properties:
29 compatible:
30 contains:
31 const: riscv
32
33 properties:
34 riscv,isa:
35 description:
36 Identifies the specific RISC-V instructi
37 supported by the hart. These are docume
38 User-Level ISA document, available from
39 https://riscv.org/specifications/
40
41 Due to revisions of the ISA specificatio
42 have arisen over time.
43 Notably, riscv,isa was defined prior to
44 Zicntr, Zicsr, Zifencei and Zihpm extens
45 implies "zicntr_zicsr_zifencei_zihpm".
46
47 While the isa strings in ISA specificati
48 insensitive, letters in the riscv,isa st
49 lowercase.
50 $ref: /schemas/types.yaml#/definitions/str
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?
52 deprecated: true
53
54 riscv,isa-base:
55 description:
56 The base ISA implemented by this hart, a
57 version of the unprivileged ISA specific
58 enum:
59 - rv32i
60 - rv64i
61
62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/str
64 minItems: 1
65 description: Extensions supported by the h
66 items:
67 anyOf:
68 # single letter extensions, in canonic
69 - const: i
70 description: |
71 The base integer instruction set,
72 version of the unprivileged ISA sp
73
74 This does not include Chapter 10,
75 the Zicntr and Zihpm extensions af
76 20191213 version of the unprivileg
77
78 - const: m
79 description:
80 The standard M extension for integ
81 ratified in the 20191213 version o
82 specification.
83
84 - const: a
85 description:
86 The standard A extension for atomi
87 20191213 version of the unprivileg
88
89 - const: f
90 description:
91 The standard F extension for singl
92 ratified in the 20191213 version o
93 specification.
94
95 - const: d
96 description:
97 The standard D extension for doubl
98 ratified in the 20191213 version o
99 specification.
100
101 - const: q
102 description:
103 The standard Q extension for quad-
104 ratified in the 20191213 version o
105 specification.
106
107 - const: c
108 description:
109 The standard C extension for compr
110 the 20191213 version of the unpriv
111
112 - const: v
113 description:
114 The standard V extension for vecto
115 in-and-around commit 7a6c8ae ("Fix
116 encoding") of the riscv-v-spec.
117
118 - const: h
119 description:
120 The standard H extension for hyper
121 version of the privileged ISA spec
122
123 # multi-letter extensions, sorted alph
124 - const: smaia
125 description: |
126 The standard Smaia supervisor-leve
127 interrupt architecture for machine
128 changes to interrupts as frozen at
129 request #42 from riscv/jhauser-202
130
131 - const: smstateen
132 description: |
133 The standard Smstateen extension f
134 added by other RISC-V extensions i
135 ratified at commit a28bfae (Ratifi
136
137 - const: ssaia
138 description: |
139 The standard Ssaia supervisor-leve
140 interrupt architecture for supervi
141 behavioural changes to interrupts
142 ("Merge pull request #42 from risc
143
144 - const: sscofpmf
145 description: |
146 The standard Sscofpmf supervisor-l
147 and mode-based filtering as ratifi
148 to manually trigger workflow. (#2)
149
150 - const: sstc
151 description: |
152 The standard Sstc supervisor-level
153 ratified at commit 3f9ed34 ("Add a
154 workflow. (#2)") of riscv-time-com
155
156 - const: svinval
157 description:
158 The standard Svinval supervisor-le
159 address-translation cache invalida
160 version of the privileged ISA spec
161
162 - const: svnapot
163 description:
164 The standard Svnapot supervisor-le
165 translation contiguity as ratified
166 privileged ISA specification.
167
168 - const: svpbmt
169 description:
170 The standard Svpbmt supervisor-lev
171 memory types as ratified in the 20
172 ISA specification.
173
174 - const: svvptc
175 description:
176 The standard Svvptc supervisor-lev
177 address-translation cache behaviou
178 as ratified at commit 4a69197e5617
179 riscv-svvptc.
180
181 - const: zacas
182 description: |
183 The Zacas extension for Atomic Com
184 is supported as ratified at commit
185 ratified") of the riscv-zacas.
186
187 - const: zawrs
188 description: |
189 The Zawrs extension for entering a
190 to a hypervisor while waiting on a
191 ratified in commit 98918c844281 ("
192 riscv/zawrs") of riscv-isa-manual.
193
194 - const: zba
195 description: |
196 The standard Zba bit-manipulation
197 acceleration instructions as ratif
198 request #158 from hirooih/clmul-fi
199 riscv-bitmanip.
200
201 - const: zbb
202 description: |
203 The standard Zbb bit-manipulation
204 as ratified at commit 6d33919 ("Me
205 hirooih/clmul-fix-loop-end-conditi
206
207 - const: zbc
208 description: |
209 The standard Zbc bit-manipulation
210 multiplication as ratified at comm
211 #158 from hirooih/clmul-fix-loop-e
212
213 - const: zbkb
214 description:
215 The standard Zbkb bitmanip instruc
216 in version 1.0 of RISC-V Cryptogra
217 specification.
218
219 - const: zbkc
220 description:
221 The standard Zbkc carry-less multi
222 in version 1.0 of RISC-V Cryptogra
223 specification.
224
225 - const: zbkx
226 description:
227 The standard Zbkx crossbar permuta
228 in version 1.0 of RISC-V Cryptogra
229 specification.
230
231 - const: zbs
232 description: |
233 The standard Zbs bit-manipulation
234 instructions as ratified at commit
235 from hirooih/clmul-fix-loop-end-co
236
237 - const: zca
238 description: |
239 The Zca extension part of Zc* stan
240 reduction, as ratified in commit 8
241 RV64 as it contains no instruction
242 merged in the riscv-isa-manual by
243 of zc.adoc to src tree.").
244
245 - const: zcb
246 description: |
247 The Zcb extension part of Zc* stan
248 reduction, as ratified in commit 8
249 RV64 as it contains no instruction
250 merged in the riscv-isa-manual by
251 of zc.adoc to src tree.").
252
253 - const: zcd
254 description: |
255 The Zcd extension part of Zc* stan
256 reduction, as ratified in commit 8
257 RV64 as it contains no instruction
258 merged in the riscv-isa-manual by
259 of zc.adoc to src tree.").
260
261 - const: zcf
262 description: |
263 The Zcf extension part of Zc* stan
264 reduction, as ratified in commit 8
265 RV64 as it contains no instruction
266 merged in the riscv-isa-manual by
267 of zc.adoc to src tree.").
268
269 - const: zcmop
270 description:
271 The standard Zcmop extension versi
272 c732a4f39a4 ("Zcmop is ratified/1.
273
274 - const: zfa
275 description:
276 The standard Zfa extension for add
277 instructions, as ratified in commi
278 riscv-isa-manual.
279
280 - const: zfh
281 description:
282 The standard Zfh extension for 16-
283 floating-point instructions, as ra
284 version numbers for Zfh/Zfinx") of
285
286 - const: zfhmin
287 description:
288 The standard Zfhmin extension whic
289 16-bit half-precision binary float
290 in commit 64074bc ("Update version
291 riscv-isa-manual.
292
293 - const: zk
294 description:
295 The standard Zk Standard Scalar cr
296 in version 1.0 of RISC-V Cryptogra
297 specification.
298
299 - const: zkn
300 description:
301 The standard Zkn NIST algorithm su
302 version 1.0 of RISC-V Cryptography
303 specification.
304
305 - const: zknd
306 description: |
307 The standard Zknd for NIST suite:
308 ratified in version 1.0 of RISC-V
309 specification.
310
311 - const: zkne
312 description: |
313 The standard Zkne for NIST suite:
314 ratified in version 1.0 of RISC-V
315 specification.
316
317 - const: zknh
318 description: |
319 The standard Zknh for NIST suite:
320 ratified in version 1.0 of RISC-V
321 specification.
322
323 - const: zkr
324 description:
325 The standard Zkr entropy source ex
326 1.0 of RISC-V Cryptography Extensi
327 This string being present means th
328 extension is accessible at the pri
329 device-tree has been provided.
330
331 - const: zks
332 description:
333 The standard Zks ShangMi algorithm
334 version 1.0 of RISC-V Cryptography
335 specification.
336
337 - const: zksed
338 description: |
339 The standard Zksed for ShangMi sui
340 as ratified in version 1.0 of RISC
341 Volume I specification.
342
343 - const: zksh
344 description: |
345 The standard Zksh for ShangMi suit
346 as ratified in version 1.0 of RISC
347 Volume I specification.
348
349 - const: zkt
350 description:
351 The standard Zkt for data independ
352 in version 1.0 of RISC-V Cryptogra
353 specification.
354
355 - const: zicbom
356 description:
357 The standard Zicbom extension for
358 ratified in commit 3dd606f ("Creat
359
360 - const: zicbop
361 description:
362 The standard Zicbop extension for
363 as ratified in commit 3dd606f ("Cr
364 riscv-CMOs.
365
366 - const: zicboz
367 description:
368 The standard Zicboz extension for
369 in commit 3dd606f ("Create cmobase
370
371 - const: zicntr
372 description:
373 The standard Zicntr extension for
374 ratified in the 20191213 version o
375 specification.
376
377 - const: zicond
378 description:
379 The standard Zicond extension for
380 conditional-select/move operations
381 ("Add changes requested by Ved dur
382
383 - const: zicsr
384 description: |
385 The standard Zicsr extension for c
386 instructions, as ratified in the 2
387 unprivileged ISA specification.
388
389 This does not include Chapter 10,
390 special case read-only CSRs, that
391 Zihpm extensions after the ratific
392 the unprivileged specification.
393
394 - const: zifencei
395 description:
396 The standard Zifencei extension fo
397 ratified in the 20191213 version o
398 specification.
399
400 - const: zihintpause
401 description:
402 The standard Zihintpause extension
403 commit d8ab5c7 ("Zihintpause is ra
404
405 - const: zihintntl
406 description:
407 The standard Zihintntl extension f
408 ratified in commit 0dc91f5 ("Zihin
409 riscv-isa-manual.
410
411 - const: zihpm
412 description:
413 The standard Zihpm extension for h
414 ratified in the 20191213 version o
415 specification.
416
417 - const: zimop
418 description:
419 The standard Zimop extension versi
420 58220614a5f ("Zimop is ratified/1.
421
422 - const: ztso
423 description:
424 The standard Ztso extension for to
425 in commit 2e5236 ("Ztso is now rat
426 riscv-isa-manual.
427
428 - const: zvbb
429 description:
430 The standard Zvbb extension for ve
431 instructions, as ratified in commi
432 riscv-crypto-spec-vector.adoc") of
433
434 - const: zvbc
435 description:
436 The standard Zvbc extension for ve
437 instructions, as ratified in commi
438 riscv-crypto-spec-vector.adoc") of
439
440 - const: zve32f
441 description:
442 The standard Zve32f extension for
443 in commit 6f702a2 ("Vector extensi
444 riscv-v-spec.
445
446 - const: zve32x
447 description:
448 The standard Zve32x extension for
449 in commit 6f702a2 ("Vector extensi
450 riscv-v-spec.
451
452 - const: zve64d
453 description:
454 The standard Zve64d extension for
455 in commit 6f702a2 ("Vector extensi
456 riscv-v-spec.
457
458 - const: zve64f
459 description:
460 The standard Zve64f extension for
461 in commit 6f702a2 ("Vector extensi
462 riscv-v-spec.
463
464 - const: zve64x
465 description:
466 The standard Zve64x extension for
467 in commit 6f702a2 ("Vector extensi
468 riscv-v-spec.
469
470 - const: zvfh
471 description:
472 The standard Zvfh extension for ve
473 floating-point instructions, as ra
474 ("Remove draft warnings from Zvfh[
475
476 - const: zvfhmin
477 description:
478 The standard Zvfhmin extension for
479 floating-point instructions, as ra
480 ("Remove draft warnings from Zvfh[
481
482 - const: zvkb
483 description:
484 The standard Zvkb extension for ve
485 instructions, as ratified in commi
486 riscv-crypto-spec-vector.adoc") of
487
488 - const: zvkg
489 description:
490 The standard Zvkg extension for ve
491 ratified in commit 56ed795 ("Updat
492 of riscv-crypto.
493
494 - const: zvkn
495 description:
496 The standard Zvkn extension for NI
497 ratified in commit 56ed795 ("Updat
498 of riscv-crypto.
499
500 - const: zvknc
501 description:
502 The standard Zvknc extension for N
503 multiply instructions, as ratified
504 riscv-crypto-spec-vector.adoc") of
505
506 - const: zvkned
507 description:
508 The standard Zvkned extension for
509 instructions, as ratified in commi
510 riscv-crypto-spec-vector.adoc") of
511
512 - const: zvkng
513 description:
514 The standard Zvkng extension for N
515 instructions, as ratified in commi
516 riscv-crypto-spec-vector.adoc") of
517
518 - const: zvknha
519 description: |
520 The standard Zvknha extension for
521 hash (SHA-256 only) instructions,
522 56ed795 ("Update riscv-crypto-spec
523
524 - const: zvknhb
525 description: |
526 The standard Zvknhb extension for
527 hash (SHA-256 and SHA-512) instruc
528 56ed795 ("Update riscv-crypto-spec
529
530 - const: zvks
531 description:
532 The standard Zvks extension for Sh
533 instructions, as ratified in commi
534 riscv-crypto-spec-vector.adoc") of
535
536 - const: zvksc
537 description:
538 The standard Zvksc extension for S
539 carryless multiplication instructi
540 ("Update riscv-crypto-spec-vector.
541
542 - const: zvksed
543 description: |
544 The standard Zvksed extension for
545 instructions, as ratified in commi
546 riscv-crypto-spec-vector.adoc") of
547
548 - const: zvksh
549 description: |
550 The standard Zvksh extension for S
551 instructions, as ratified in commi
552 riscv-crypto-spec-vector.adoc") of
553
554 - const: zvksg
555 description:
556 The standard Zvksg extension for S
557 instructions, as ratified in commi
558 riscv-crypto-spec-vector.adoc") of
559
560 - const: zvkt
561 description:
562 The standard Zvkt extension for ve
563 latency, as ratified in commit 56e
564 riscv-crypto-spec-vector.adoc") of
565
566 - const: xandespmu
567 description:
568 The Andes Technology performance m
569 and privilege mode filtering. For
570 Registers in the AX45MP datasheet.
571 https://www.andestech.com/wp-conte
572
573 allOf:
574 # Zcb depends on Zca
575 - if:
576 contains:
577 const: zcb
578 then:
579 contains:
580 const: zca
581 # Zcd depends on Zca and D
582 - if:
583 contains:
584 const: zcd
585 then:
586 allOf:
587 - contains:
588 const: zca
589 - contains:
590 const: d
591 # Zcf depends on Zca and F
592 - if:
593 contains:
594 const: zcf
595 then:
596 allOf:
597 - contains:
598 const: zca
599 - contains:
600 const: f
601 # Zcmop depends on Zca
602 - if:
603 contains:
604 const: zcmop
605 then:
606 contains:
607 const: zca
608
609 allOf:
610 # Zcf extension does not exist on rv64
611 - if:
612 properties:
613 riscv,isa-extensions:
614 contains:
615 const: zcf
616 riscv,isa-base:
617 contains:
618 const: rv64i
619 then:
620 properties:
621 riscv,isa-extensions:
622 not:
623 contains:
624 const: zcf
625
626 additionalProperties: true
627 ...
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