1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/riscv/exten 4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: RISC-V ISA extensions 7 title: RISC-V ISA extensions
8 8
9 maintainers: 9 maintainers:
10 - Paul Walmsley <paul.walmsley@sifive.com> 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org> 12 - Conor Dooley <conor@kernel.org>
13 13
14 description: | 14 description: |
15 RISC-V has a large number of extensions, som 15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RIS 16 extensions, meaning they are ratified by RISC-V International, and others
17 are "vendor" extensions. 17 are "vendor" extensions.
18 This document defines properties that indica 18 This document defines properties that indicate whether a hart supports a
19 given extension. 19 given extension.
20 20
21 Once a standard extension has been ratified, 21 Once a standard extension has been ratified, no changes in behaviour can be
22 made without the creation of a new extension 22 made without the creation of a new extension.
23 The properties for standard extensions there 23 The properties for standard extensions therefore map to their originally
24 ratified states, with the exception of the I 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions.
25 See the "i" property for more information. 25 See the "i" property for more information.
26 26
27 select: 27 select:
28 properties: 28 properties:
29 compatible: 29 compatible:
30 contains: 30 contains:
31 const: riscv 31 const: riscv
32 32
33 properties: 33 properties:
34 riscv,isa: 34 riscv,isa:
35 description: 35 description:
36 Identifies the specific RISC-V instructi 36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are docume 37 supported by the hart. These are documented in the RISC-V
38 User-Level ISA document, available from 38 User-Level ISA document, available from
39 https://riscv.org/specifications/ 39 https://riscv.org/specifications/
40 40
41 Due to revisions of the ISA specificatio 41 Due to revisions of the ISA specification, some deviations
42 have arisen over time. 42 have arisen over time.
43 Notably, riscv,isa was defined prior to 43 Notably, riscv,isa was defined prior to the creation of the
44 Zicntr, Zicsr, Zifencei and Zihpm extens 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
45 implies "zicntr_zicsr_zifencei_zihpm". 45 implies "zicntr_zicsr_zifencei_zihpm".
46 46
47 While the isa strings in ISA specificati 47 While the isa strings in ISA specification are case
48 insensitive, letters in the riscv,isa st 48 insensitive, letters in the riscv,isa string must be all
49 lowercase. 49 lowercase.
50 $ref: /schemas/types.yaml#/definitions/str 50 $ref: /schemas/types.yaml#/definitions/string
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v? !! 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
52 deprecated: true 52 deprecated: true
53 53
54 riscv,isa-base: 54 riscv,isa-base:
55 description: 55 description:
56 The base ISA implemented by this hart, a 56 The base ISA implemented by this hart, as described by the 20191213
57 version of the unprivileged ISA specific 57 version of the unprivileged ISA specification.
58 enum: 58 enum:
59 - rv32i 59 - rv32i
60 - rv64i 60 - rv64i
61 61
62 riscv,isa-extensions: 62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/str 63 $ref: /schemas/types.yaml#/definitions/string-array
64 minItems: 1 64 minItems: 1
65 description: Extensions supported by the h 65 description: Extensions supported by the hart.
66 items: 66 items:
67 anyOf: 67 anyOf:
68 # single letter extensions, in canonic 68 # single letter extensions, in canonical order
69 - const: i 69 - const: i
70 description: | 70 description: |
71 The base integer instruction set, 71 The base integer instruction set, as ratified in the 20191213
72 version of the unprivileged ISA sp 72 version of the unprivileged ISA specification.
73 73
74 This does not include Chapter 10, 74 This does not include Chapter 10, "Counters", which was moved into
75 the Zicntr and Zihpm extensions af 75 the Zicntr and Zihpm extensions after the ratification of the
76 20191213 version of the unprivileg 76 20191213 version of the unprivileged specification.
77 77
78 - const: m 78 - const: m
79 description: 79 description:
80 The standard M extension for integ 80 The standard M extension for integer multiplication and division, as
81 ratified in the 20191213 version o 81 ratified in the 20191213 version of the unprivileged ISA
82 specification. 82 specification.
83 83
84 - const: a 84 - const: a
85 description: 85 description:
86 The standard A extension for atomi 86 The standard A extension for atomic instructions, as ratified in the
87 20191213 version of the unprivileg 87 20191213 version of the unprivileged ISA specification.
88 88
89 - const: f 89 - const: f
90 description: 90 description:
91 The standard F extension for singl 91 The standard F extension for single-precision floating point, as
92 ratified in the 20191213 version o 92 ratified in the 20191213 version of the unprivileged ISA
93 specification. 93 specification.
94 94
95 - const: d 95 - const: d
96 description: 96 description:
97 The standard D extension for doubl 97 The standard D extension for double-precision floating-point, as
98 ratified in the 20191213 version o 98 ratified in the 20191213 version of the unprivileged ISA
99 specification. 99 specification.
100 100
101 - const: q 101 - const: q
102 description: 102 description:
103 The standard Q extension for quad- 103 The standard Q extension for quad-precision floating-point, as
104 ratified in the 20191213 version o 104 ratified in the 20191213 version of the unprivileged ISA
105 specification. 105 specification.
106 106
107 - const: c 107 - const: c
108 description: 108 description:
109 The standard C extension for compr 109 The standard C extension for compressed instructions, as ratified in
110 the 20191213 version of the unpriv 110 the 20191213 version of the unprivileged ISA specification.
111 111
112 - const: v 112 - const: v
113 description: 113 description:
114 The standard V extension for vecto 114 The standard V extension for vector operations, as ratified
115 in-and-around commit 7a6c8ae ("Fix 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116 encoding") of the riscv-v-spec. 116 encoding") of the riscv-v-spec.
117 117
118 - const: h 118 - const: h
119 description: 119 description:
120 The standard H extension for hyper 120 The standard H extension for hypervisors as ratified in the 20191213
121 version of the privileged ISA spec 121 version of the privileged ISA specification.
122 122
123 # multi-letter extensions, sorted alph 123 # multi-letter extensions, sorted alphanumerically
124 - const: smaia 124 - const: smaia
125 description: | 125 description: |
126 The standard Smaia supervisor-leve 126 The standard Smaia supervisor-level extension for the advanced
127 interrupt architecture for machine 127 interrupt architecture for machine-mode-visible csr and behavioural
128 changes to interrupts as frozen at 128 changes to interrupts as frozen at commit ccbddab ("Merge pull
129 request #42 from riscv/jhauser-202 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
130 130
131 - const: smstateen <<
132 description: | <<
133 The standard Smstateen extension f <<
134 added by other RISC-V extensions i <<
135 ratified at commit a28bfae (Ratifi <<
136 <<
137 - const: ssaia 131 - const: ssaia
138 description: | 132 description: |
139 The standard Ssaia supervisor-leve 133 The standard Ssaia supervisor-level extension for the advanced
140 interrupt architecture for supervi 134 interrupt architecture for supervisor-mode-visible csr and
141 behavioural changes to interrupts 135 behavioural changes to interrupts as frozen at commit ccbddab
142 ("Merge pull request #42 from risc 136 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
143 137
144 - const: sscofpmf 138 - const: sscofpmf
145 description: | 139 description: |
146 The standard Sscofpmf supervisor-l 140 The standard Sscofpmf supervisor-level extension for count overflow
147 and mode-based filtering as ratifi 141 and mode-based filtering as ratified at commit 01d1df0 ("Add ability
148 to manually trigger workflow. (#2) 142 to manually trigger workflow. (#2)") of riscv-count-overflow.
149 143
150 - const: sstc 144 - const: sstc
151 description: | 145 description: |
152 The standard Sstc supervisor-level 146 The standard Sstc supervisor-level extension for time compare as
153 ratified at commit 3f9ed34 ("Add a 147 ratified at commit 3f9ed34 ("Add ability to manually trigger
154 workflow. (#2)") of riscv-time-com 148 workflow. (#2)") of riscv-time-compare.
155 149
156 - const: svinval 150 - const: svinval
157 description: 151 description:
158 The standard Svinval supervisor-le 152 The standard Svinval supervisor-level extension for fine-grained
159 address-translation cache invalida 153 address-translation cache invalidation as ratified in the 20191213
160 version of the privileged ISA spec 154 version of the privileged ISA specification.
161 155
162 - const: svnapot 156 - const: svnapot
163 description: 157 description:
164 The standard Svnapot supervisor-le 158 The standard Svnapot supervisor-level extensions for napot
165 translation contiguity as ratified 159 translation contiguity as ratified in the 20191213 version of the
166 privileged ISA specification. 160 privileged ISA specification.
167 161
168 - const: svpbmt 162 - const: svpbmt
169 description: 163 description:
170 The standard Svpbmt supervisor-lev 164 The standard Svpbmt supervisor-level extensions for page-based
171 memory types as ratified in the 20 165 memory types as ratified in the 20191213 version of the privileged
172 ISA specification. 166 ISA specification.
173 167
174 - const: svvptc <<
175 description: <<
176 The standard Svvptc supervisor-lev <<
177 address-translation cache behaviou <<
178 as ratified at commit 4a69197e5617 <<
179 riscv-svvptc. <<
180 <<
181 - const: zacas <<
182 description: | <<
183 The Zacas extension for Atomic Com <<
184 is supported as ratified at commit <<
185 ratified") of the riscv-zacas. <<
186 <<
187 - const: zawrs <<
188 description: | <<
189 The Zawrs extension for entering a <<
190 to a hypervisor while waiting on a <<
191 ratified in commit 98918c844281 (" <<
192 riscv/zawrs") of riscv-isa-manual. <<
193 <<
194 - const: zba 168 - const: zba
195 description: | 169 description: |
196 The standard Zba bit-manipulation 170 The standard Zba bit-manipulation extension for address generation
197 acceleration instructions as ratif 171 acceleration instructions as ratified at commit 6d33919 ("Merge pull
198 request #158 from hirooih/clmul-fi 172 request #158 from hirooih/clmul-fix-loop-end-condition") of
199 riscv-bitmanip. 173 riscv-bitmanip.
200 174
201 - const: zbb 175 - const: zbb
202 description: | 176 description: |
203 The standard Zbb bit-manipulation 177 The standard Zbb bit-manipulation extension for basic bit-manipulation
204 as ratified at commit 6d33919 ("Me 178 as ratified at commit 6d33919 ("Merge pull request #158 from
205 hirooih/clmul-fix-loop-end-conditi 179 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
206 180
207 - const: zbc 181 - const: zbc
208 description: | 182 description: |
209 The standard Zbc bit-manipulation 183 The standard Zbc bit-manipulation extension for carry-less
210 multiplication as ratified at comm 184 multiplication as ratified at commit 6d33919 ("Merge pull request
211 #158 from hirooih/clmul-fix-loop-e 185 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
212 186
213 - const: zbkb <<
214 description: <<
215 The standard Zbkb bitmanip instruc <<
216 in version 1.0 of RISC-V Cryptogra <<
217 specification. <<
218 <<
219 - const: zbkc <<
220 description: <<
221 The standard Zbkc carry-less multi <<
222 in version 1.0 of RISC-V Cryptogra <<
223 specification. <<
224 <<
225 - const: zbkx <<
226 description: <<
227 The standard Zbkx crossbar permuta <<
228 in version 1.0 of RISC-V Cryptogra <<
229 specification. <<
230 <<
231 - const: zbs 187 - const: zbs
232 description: | 188 description: |
233 The standard Zbs bit-manipulation 189 The standard Zbs bit-manipulation extension for single-bit
234 instructions as ratified at commit 190 instructions as ratified at commit 6d33919 ("Merge pull request #158
235 from hirooih/clmul-fix-loop-end-co 191 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
236 192
237 - const: zca <<
238 description: | <<
239 The Zca extension part of Zc* stan <<
240 reduction, as ratified in commit 8 <<
241 RV64 as it contains no instruction <<
242 merged in the riscv-isa-manual by <<
243 of zc.adoc to src tree."). <<
244 <<
245 - const: zcb <<
246 description: | <<
247 The Zcb extension part of Zc* stan <<
248 reduction, as ratified in commit 8 <<
249 RV64 as it contains no instruction <<
250 merged in the riscv-isa-manual by <<
251 of zc.adoc to src tree."). <<
252 <<
253 - const: zcd <<
254 description: | <<
255 The Zcd extension part of Zc* stan <<
256 reduction, as ratified in commit 8 <<
257 RV64 as it contains no instruction <<
258 merged in the riscv-isa-manual by <<
259 of zc.adoc to src tree."). <<
260 <<
261 - const: zcf <<
262 description: | <<
263 The Zcf extension part of Zc* stan <<
264 reduction, as ratified in commit 8 <<
265 RV64 as it contains no instruction <<
266 merged in the riscv-isa-manual by <<
267 of zc.adoc to src tree."). <<
268 <<
269 - const: zcmop <<
270 description: <<
271 The standard Zcmop extension versi <<
272 c732a4f39a4 ("Zcmop is ratified/1. <<
273 <<
274 - const: zfa <<
275 description: <<
276 The standard Zfa extension for add <<
277 instructions, as ratified in commi <<
278 riscv-isa-manual. <<
279 <<
280 - const: zfh <<
281 description: <<
282 The standard Zfh extension for 16- <<
283 floating-point instructions, as ra <<
284 version numbers for Zfh/Zfinx") of <<
285 <<
286 - const: zfhmin <<
287 description: <<
288 The standard Zfhmin extension whic <<
289 16-bit half-precision binary float <<
290 in commit 64074bc ("Update version <<
291 riscv-isa-manual. <<
292 <<
293 - const: zk <<
294 description: <<
295 The standard Zk Standard Scalar cr <<
296 in version 1.0 of RISC-V Cryptogra <<
297 specification. <<
298 <<
299 - const: zkn <<
300 description: <<
301 The standard Zkn NIST algorithm su <<
302 version 1.0 of RISC-V Cryptography <<
303 specification. <<
304 <<
305 - const: zknd <<
306 description: | <<
307 The standard Zknd for NIST suite: <<
308 ratified in version 1.0 of RISC-V <<
309 specification. <<
310 <<
311 - const: zkne <<
312 description: | <<
313 The standard Zkne for NIST suite: <<
314 ratified in version 1.0 of RISC-V <<
315 specification. <<
316 <<
317 - const: zknh <<
318 description: | <<
319 The standard Zknh for NIST suite: <<
320 ratified in version 1.0 of RISC-V <<
321 specification. <<
322 <<
323 - const: zkr <<
324 description: <<
325 The standard Zkr entropy source ex <<
326 1.0 of RISC-V Cryptography Extensi <<
327 This string being present means th <<
328 extension is accessible at the pri <<
329 device-tree has been provided. <<
330 <<
331 - const: zks <<
332 description: <<
333 The standard Zks ShangMi algorithm <<
334 version 1.0 of RISC-V Cryptography <<
335 specification. <<
336 <<
337 - const: zksed <<
338 description: | <<
339 The standard Zksed for ShangMi sui <<
340 as ratified in version 1.0 of RISC <<
341 Volume I specification. <<
342 <<
343 - const: zksh <<
344 description: | <<
345 The standard Zksh for ShangMi suit <<
346 as ratified in version 1.0 of RISC <<
347 Volume I specification. <<
348 <<
349 - const: zkt <<
350 description: <<
351 The standard Zkt for data independ <<
352 in version 1.0 of RISC-V Cryptogra <<
353 specification. <<
354 <<
355 - const: zicbom 193 - const: zicbom
356 description: 194 description:
357 The standard Zicbom extension for 195 The standard Zicbom extension for base cache management operations as
358 ratified in commit 3dd606f ("Creat 196 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
359 197
360 - const: zicbop 198 - const: zicbop
361 description: 199 description:
362 The standard Zicbop extension for 200 The standard Zicbop extension for cache-block prefetch instructions
363 as ratified in commit 3dd606f ("Cr 201 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
364 riscv-CMOs. 202 riscv-CMOs.
365 203
366 - const: zicboz 204 - const: zicboz
367 description: 205 description:
368 The standard Zicboz extension for 206 The standard Zicboz extension for cache-block zeroing as ratified
369 in commit 3dd606f ("Create cmobase 207 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
370 208
371 - const: zicntr 209 - const: zicntr
372 description: 210 description:
373 The standard Zicntr extension for 211 The standard Zicntr extension for base counters and timers, as
374 ratified in the 20191213 version o 212 ratified in the 20191213 version of the unprivileged ISA
375 specification. 213 specification.
376 214
377 - const: zicond <<
378 description: <<
379 The standard Zicond extension for <<
380 conditional-select/move operations <<
381 ("Add changes requested by Ved dur <<
382 <<
383 - const: zicsr 215 - const: zicsr
384 description: | 216 description: |
385 The standard Zicsr extension for c 217 The standard Zicsr extension for control and status register
386 instructions, as ratified in the 2 218 instructions, as ratified in the 20191213 version of the
387 unprivileged ISA specification. 219 unprivileged ISA specification.
388 220
389 This does not include Chapter 10, 221 This does not include Chapter 10, "Counters", which documents
390 special case read-only CSRs, that 222 special case read-only CSRs, that were moved into the Zicntr and
391 Zihpm extensions after the ratific 223 Zihpm extensions after the ratification of the 20191213 version of
392 the unprivileged specification. 224 the unprivileged specification.
393 225
394 - const: zifencei 226 - const: zifencei
395 description: 227 description:
396 The standard Zifencei extension fo 228 The standard Zifencei extension for instruction-fetch fence, as
397 ratified in the 20191213 version o 229 ratified in the 20191213 version of the unprivileged ISA
398 specification. 230 specification.
399 231
400 - const: zihintpause 232 - const: zihintpause
401 description: 233 description:
402 The standard Zihintpause extension 234 The standard Zihintpause extension for pause hints, as ratified in
403 commit d8ab5c7 ("Zihintpause is ra 235 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
404 236
405 - const: zihintntl <<
406 description: <<
407 The standard Zihintntl extension f <<
408 ratified in commit 0dc91f5 ("Zihin <<
409 riscv-isa-manual. <<
410 <<
411 - const: zihpm 237 - const: zihpm
412 description: 238 description:
413 The standard Zihpm extension for h 239 The standard Zihpm extension for hardware performance counters, as
414 ratified in the 20191213 version o 240 ratified in the 20191213 version of the unprivileged ISA
415 specification. 241 specification.
416 242
417 - const: zimop <<
418 description: <<
419 The standard Zimop extension versi <<
420 58220614a5f ("Zimop is ratified/1. <<
421 <<
422 - const: ztso 243 - const: ztso
423 description: 244 description:
424 The standard Ztso extension for to 245 The standard Ztso extension for total store ordering, as ratified
425 in commit 2e5236 ("Ztso is now rat 246 in commit 2e5236 ("Ztso is now ratified.") of the
426 riscv-isa-manual. 247 riscv-isa-manual.
427 <<
428 - const: zvbb <<
429 description: <<
430 The standard Zvbb extension for ve <<
431 instructions, as ratified in commi <<
432 riscv-crypto-spec-vector.adoc") of <<
433 <<
434 - const: zvbc <<
435 description: <<
436 The standard Zvbc extension for ve <<
437 instructions, as ratified in commi <<
438 riscv-crypto-spec-vector.adoc") of <<
439 <<
440 - const: zve32f <<
441 description: <<
442 The standard Zve32f extension for <<
443 in commit 6f702a2 ("Vector extensi <<
444 riscv-v-spec. <<
445 <<
446 - const: zve32x <<
447 description: <<
448 The standard Zve32x extension for <<
449 in commit 6f702a2 ("Vector extensi <<
450 riscv-v-spec. <<
451 <<
452 - const: zve64d <<
453 description: <<
454 The standard Zve64d extension for <<
455 in commit 6f702a2 ("Vector extensi <<
456 riscv-v-spec. <<
457 <<
458 - const: zve64f <<
459 description: <<
460 The standard Zve64f extension for <<
461 in commit 6f702a2 ("Vector extensi <<
462 riscv-v-spec. <<
463 <<
464 - const: zve64x <<
465 description: <<
466 The standard Zve64x extension for <<
467 in commit 6f702a2 ("Vector extensi <<
468 riscv-v-spec. <<
469 <<
470 - const: zvfh <<
471 description: <<
472 The standard Zvfh extension for ve <<
473 floating-point instructions, as ra <<
474 ("Remove draft warnings from Zvfh[ <<
475 <<
476 - const: zvfhmin <<
477 description: <<
478 The standard Zvfhmin extension for <<
479 floating-point instructions, as ra <<
480 ("Remove draft warnings from Zvfh[ <<
481 <<
482 - const: zvkb <<
483 description: <<
484 The standard Zvkb extension for ve <<
485 instructions, as ratified in commi <<
486 riscv-crypto-spec-vector.adoc") of <<
487 <<
488 - const: zvkg <<
489 description: <<
490 The standard Zvkg extension for ve <<
491 ratified in commit 56ed795 ("Updat <<
492 of riscv-crypto. <<
493 <<
494 - const: zvkn <<
495 description: <<
496 The standard Zvkn extension for NI <<
497 ratified in commit 56ed795 ("Updat <<
498 of riscv-crypto. <<
499 <<
500 - const: zvknc <<
501 description: <<
502 The standard Zvknc extension for N <<
503 multiply instructions, as ratified <<
504 riscv-crypto-spec-vector.adoc") of <<
505 <<
506 - const: zvkned <<
507 description: <<
508 The standard Zvkned extension for <<
509 instructions, as ratified in commi <<
510 riscv-crypto-spec-vector.adoc") of <<
511 <<
512 - const: zvkng <<
513 description: <<
514 The standard Zvkng extension for N <<
515 instructions, as ratified in commi <<
516 riscv-crypto-spec-vector.adoc") of <<
517 <<
518 - const: zvknha <<
519 description: | <<
520 The standard Zvknha extension for <<
521 hash (SHA-256 only) instructions, <<
522 56ed795 ("Update riscv-crypto-spec <<
523 <<
524 - const: zvknhb <<
525 description: | <<
526 The standard Zvknhb extension for <<
527 hash (SHA-256 and SHA-512) instruc <<
528 56ed795 ("Update riscv-crypto-spec <<
529 <<
530 - const: zvks <<
531 description: <<
532 The standard Zvks extension for Sh <<
533 instructions, as ratified in commi <<
534 riscv-crypto-spec-vector.adoc") of <<
535 <<
536 - const: zvksc <<
537 description: <<
538 The standard Zvksc extension for S <<
539 carryless multiplication instructi <<
540 ("Update riscv-crypto-spec-vector. <<
541 <<
542 - const: zvksed <<
543 description: | <<
544 The standard Zvksed extension for <<
545 instructions, as ratified in commi <<
546 riscv-crypto-spec-vector.adoc") of <<
547 <<
548 - const: zvksh <<
549 description: | <<
550 The standard Zvksh extension for S <<
551 instructions, as ratified in commi <<
552 riscv-crypto-spec-vector.adoc") of <<
553 <<
554 - const: zvksg <<
555 description: <<
556 The standard Zvksg extension for S <<
557 instructions, as ratified in commi <<
558 riscv-crypto-spec-vector.adoc") of <<
559 <<
560 - const: zvkt <<
561 description: <<
562 The standard Zvkt extension for ve <<
563 latency, as ratified in commit 56e <<
564 riscv-crypto-spec-vector.adoc") of <<
565 <<
566 - const: xandespmu <<
567 description: <<
568 The Andes Technology performance m <<
569 and privilege mode filtering. For <<
570 Registers in the AX45MP datasheet. <<
571 https://www.andestech.com/wp-conte <<
572 <<
573 allOf: <<
574 # Zcb depends on Zca <<
575 - if: <<
576 contains: <<
577 const: zcb <<
578 then: <<
579 contains: <<
580 const: zca <<
581 # Zcd depends on Zca and D <<
582 - if: <<
583 contains: <<
584 const: zcd <<
585 then: <<
586 allOf: <<
587 - contains: <<
588 const: zca <<
589 - contains: <<
590 const: d <<
591 # Zcf depends on Zca and F <<
592 - if: <<
593 contains: <<
594 const: zcf <<
595 then: <<
596 allOf: <<
597 - contains: <<
598 const: zca <<
599 - contains: <<
600 const: f <<
601 # Zcmop depends on Zca <<
602 - if: <<
603 contains: <<
604 const: zcmop <<
605 then: <<
606 contains: <<
607 const: zca <<
608 <<
609 allOf: <<
610 # Zcf extension does not exist on rv64 <<
611 - if: <<
612 properties: <<
613 riscv,isa-extensions: <<
614 contains: <<
615 const: zcf <<
616 riscv,isa-base: <<
617 contains: <<
618 const: rv64i <<
619 then: <<
620 properties: <<
621 riscv,isa-extensions: <<
622 not: <<
623 contains: <<
624 const: zcf <<
625 248
626 additionalProperties: true 249 additionalProperties: true
627 ... 250 ...
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