1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/rtc/xlnx,zy 4 $id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time 7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
8 8
9 description: 9 description:
10 RTC controller for the Xilinx Zynq MPSoC Rea 10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
11 The RTC controller has separate IRQ lines fo 11 The RTC controller has separate IRQ lines for seconds and alarm.
12 12
13 maintainers: 13 maintainers:
14 - Michal Simek <michal.simek@amd.com> !! 14 - Michal Simek <michal.simek@xilinx.com>
15 15
16 allOf: 16 allOf:
17 - $ref: rtc.yaml# 17 - $ref: rtc.yaml#
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 oneOf: !! 21 const: xlnx,zynqmp-rtc
22 - const: xlnx,zynqmp-rtc <<
23 - items: <<
24 - enum: <<
25 - xlnx,versal-rtc <<
26 - xlnx,versal-net-rtc <<
27 - const: xlnx,zynqmp-rtc <<
28 22
29 reg: 23 reg:
30 maxItems: 1 24 maxItems: 1
31 25
32 clocks: 26 clocks:
33 maxItems: 1 27 maxItems: 1
34 28
35 clock-names: 29 clock-names:
36 items: 30 items:
37 - const: rtc 31 - const: rtc
38 32
39 interrupts: 33 interrupts:
40 maxItems: 2 34 maxItems: 2
41 35
42 interrupt-names: 36 interrupt-names:
43 items: 37 items:
44 - const: alarm 38 - const: alarm
45 - const: sec 39 - const: sec
46 40
47 calibration: 41 calibration:
48 description: | 42 description: |
49 calibration value for 1 sec period which 43 calibration value for 1 sec period which will
50 be programmed directly to calibration re 44 be programmed directly to calibration register.
51 $ref: /schemas/types.yaml#/definitions/uin 45 $ref: /schemas/types.yaml#/definitions/uint32
52 minimum: 0x1 46 minimum: 0x1
53 maximum: 0x1FFFFF 47 maximum: 0x1FFFFF
54 default: 0x198233 48 default: 0x198233
55 deprecated: true 49 deprecated: true
56 <<
57 power-domains: <<
58 maxItems: 1 <<
59 50
60 required: 51 required:
61 - compatible 52 - compatible
62 - reg 53 - reg
63 - interrupts 54 - interrupts
64 - interrupt-names 55 - interrupt-names
65 56
66 additionalProperties: false 57 additionalProperties: false
67 58
68 examples: 59 examples:
69 - | 60 - |
70 soc { 61 soc {
71 #address-cells = <2>; 62 #address-cells = <2>;
72 #size-cells = <2>; 63 #size-cells = <2>;
73 64
74 rtc: rtc@ffa60000 { 65 rtc: rtc@ffa60000 {
75 compatible = "xlnx,zynqmp-rtc"; 66 compatible = "xlnx,zynqmp-rtc";
76 reg = <0x0 0xffa60000 0x0 0x100>; 67 reg = <0x0 0xffa60000 0x0 0x100>;
77 interrupt-parent = <&gic>; 68 interrupt-parent = <&gic>;
78 interrupts = <0 26 4>, <0 27 4>; 69 interrupts = <0 26 4>, <0 27 4>;
79 interrupt-names = "alarm", "sec"; 70 interrupt-names = "alarm", "sec";
80 calibration = <0x198233>; 71 calibration = <0x198233>;
81 clock-names = "rtc"; 72 clock-names = "rtc";
82 clocks = <&rtc_clk>; 73 clocks = <&rtc_clk>;
83 }; 74 };
84 }; 75 };
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