1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk 1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/serial/8250 4 $id: http://devicetree.org/schemas/serial/8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: UART (Universal Asynchronous Receiver/T 7 title: UART (Universal Asynchronous Receiver/Transmitter)
8 8
9 maintainers: 9 maintainers:
10 - devicetree@vger.kernel.org 10 - devicetree@vger.kernel.org
11 11
12 allOf: 12 allOf:
13 - $ref: serial.yaml# 13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-perip 14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if: 15 - if:
16 anyOf: 16 anyOf:
17 - required: 17 - required:
18 - aspeed,lpc-io-reg 18 - aspeed,lpc-io-reg
19 - required: 19 - required:
20 - aspeed,lpc-interrupts 20 - aspeed,lpc-interrupts
21 - required: 21 - required:
22 - aspeed,sirq-polarity-sense 22 - aspeed,sirq-polarity-sense
23 then: 23 then:
24 properties: 24 properties:
25 compatible: 25 compatible:
26 const: aspeed,ast2500-vuart 26 const: aspeed,ast2500-vuart
27 - if: 27 - if:
28 properties: 28 properties:
29 compatible: 29 compatible:
30 const: mrvl,mmp-uart 30 const: mrvl,mmp-uart
31 then: 31 then:
32 properties: 32 properties:
33 reg-shift: 33 reg-shift:
34 const: 2 34 const: 2
35 required: 35 required:
36 - reg-shift 36 - reg-shift
37 - if: 37 - if:
38 not: 38 not:
39 properties: 39 properties:
40 compatible: 40 compatible:
41 items: 41 items:
42 - enum: 42 - enum:
43 - ns8250 43 - ns8250
44 - ns16450 44 - ns16450
45 - ns16550 45 - ns16550
46 - ns16550a 46 - ns16550a
47 then: 47 then:
48 anyOf: 48 anyOf:
49 - required: [ clock-frequency ] 49 - required: [ clock-frequency ]
50 - required: [ clocks ] 50 - required: [ clocks ]
51 51
52 properties: 52 properties:
53 compatible: 53 compatible:
54 oneOf: 54 oneOf:
55 - const: ns8250 55 - const: ns8250
56 - const: ns16450 56 - const: ns16450
57 - const: ns16550 57 - const: ns16550
58 - const: ns16550a 58 - const: ns16550a
59 - const: ns16850 59 - const: ns16850
60 - const: aspeed,ast2400-vuart 60 - const: aspeed,ast2400-vuart
61 - const: aspeed,ast2500-vuart 61 - const: aspeed,ast2500-vuart
62 - const: intel,xscale-uart 62 - const: intel,xscale-uart
63 - const: mrvl,pxa-uart 63 - const: mrvl,pxa-uart
64 - const: nuvoton,wpcm450-uart 64 - const: nuvoton,wpcm450-uart
65 - const: nuvoton,npcm750-uart 65 - const: nuvoton,npcm750-uart
66 - const: nvidia,tegra20-uart 66 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart 67 - const: nxp,lpc3220-uart
68 - items: 68 - items:
69 - enum: 69 - enum:
70 - exar,xr16l2552 70 - exar,xr16l2552
71 - exar,xr16l2551 71 - exar,xr16l2551
72 - exar,xr16l2550 72 - exar,xr16l2550
73 - const: ns8250 73 - const: ns8250
74 - items: 74 - items:
75 - enum: 75 - enum:
76 - altr,16550-FIFO32 76 - altr,16550-FIFO32
77 - altr,16550-FIFO64 77 - altr,16550-FIFO64
78 - altr,16550-FIFO128 78 - altr,16550-FIFO128
79 - fsl,16550-FIFO64 79 - fsl,16550-FIFO64
80 - fsl,ns16550 80 - fsl,ns16550
81 - andestech,uart16550 81 - andestech,uart16550
82 - nxp,lpc1850-uart 82 - nxp,lpc1850-uart
83 - opencores,uart16550-rtlsvn105 83 - opencores,uart16550-rtlsvn105
84 - ti,da830-uart 84 - ti,da830-uart
85 - const: ns16550a 85 - const: ns16550a
86 - items: 86 - items:
87 - enum: 87 - enum:
88 - ns16750 88 - ns16750
89 - cavium,octeon-3860-uart 89 - cavium,octeon-3860-uart
90 - xlnx,xps-uart16550-2.00.b 90 - xlnx,xps-uart16550-2.00.b
91 - ralink,rt2880-uart 91 - ralink,rt2880-uart
92 - enum: 92 - enum:
93 - ns16550 # Deprecated, unless t 93 - ns16550 # Deprecated, unless the FIFO really is broken
94 - ns16550a 94 - ns16550a
95 - items: 95 - items:
96 - enum: 96 - enum:
97 - nuvoton,npcm845-uart 97 - nuvoton,npcm845-uart
98 - const: nuvoton,npcm750-uart 98 - const: nuvoton,npcm750-uart
99 - items: 99 - items:
100 - enum: 100 - enum:
101 - ralink,mt7620a-uart 101 - ralink,mt7620a-uart
102 - ralink,rt3052-uart 102 - ralink,rt3052-uart
103 - ralink,rt3883-uart 103 - ralink,rt3883-uart
104 - const: ralink,rt2880-uart 104 - const: ralink,rt2880-uart
105 - enum: 105 - enum:
106 - ns16550 # Deprecated, unless t 106 - ns16550 # Deprecated, unless the FIFO really is broken
107 - ns16550a 107 - ns16550a
108 - items: 108 - items:
109 - enum: 109 - enum:
110 - mediatek,mt7622-btif 110 - mediatek,mt7622-btif
111 - mediatek,mt7623-btif 111 - mediatek,mt7623-btif
112 - const: mediatek,mtk-btif 112 - const: mediatek,mtk-btif
113 - items: 113 - items:
114 - const: mrvl,mmp-uart 114 - const: mrvl,mmp-uart
115 - const: intel,xscale-uart 115 - const: intel,xscale-uart
116 - items: 116 - items:
117 - enum: 117 - enum:
118 - nvidia,tegra30-uart 118 - nvidia,tegra30-uart
119 - nvidia,tegra114-uart 119 - nvidia,tegra114-uart
120 - nvidia,tegra124-uart 120 - nvidia,tegra124-uart
121 - nvidia,tegra210-uart 121 - nvidia,tegra210-uart
122 - nvidia,tegra186-uart 122 - nvidia,tegra186-uart
123 - nvidia,tegra194-uart 123 - nvidia,tegra194-uart
124 - nvidia,tegra234-uart 124 - nvidia,tegra234-uart
125 - const: nvidia,tegra20-uart 125 - const: nvidia,tegra20-uart
126 126
127 reg: 127 reg:
128 maxItems: 1 128 maxItems: 1
129 129
130 interrupts: 130 interrupts:
131 maxItems: 1 131 maxItems: 1
132 132
133 clock-frequency: true 133 clock-frequency: true
134 134
135 clocks: 135 clocks:
136 maxItems: 1 136 maxItems: 1
137 137
138 resets: 138 resets:
139 maxItems: 1 139 maxItems: 1
140 140
141 current-speed: 141 current-speed:
142 $ref: /schemas/types.yaml#/definitions/uin 142 $ref: /schemas/types.yaml#/definitions/uint32
143 description: The current active speed of t 143 description: The current active speed of the UART.
144 144
145 reg-offset: 145 reg-offset:
146 $ref: /schemas/types.yaml#/definitions/uin 146 $ref: /schemas/types.yaml#/definitions/uint32
147 description: | 147 description: |
148 Offset to apply to the mapbase from the 148 Offset to apply to the mapbase from the start of the registers.
149 149
150 reg-shift: 150 reg-shift:
151 description: Quantity to shift the registe 151 description: Quantity to shift the register offsets by.
152 152
153 reg-io-width: 153 reg-io-width:
154 description: | 154 description: |
155 The size (in bytes) of the IO accesses t 155 The size (in bytes) of the IO accesses that should be performed on the
156 device. There are some systems that requ 156 device. There are some systems that require 32-bit accesses to the
157 UART (e.g. TI davinci). 157 UART (e.g. TI davinci).
158 158
159 used-by-rtas: 159 used-by-rtas:
160 type: boolean 160 type: boolean
161 description: | 161 description: |
162 Set to indicate that the port is in use 162 Set to indicate that the port is in use by the OpenFirmware RTAS and
163 should not be registered. 163 should not be registered.
164 164
165 no-loopback-test: 165 no-loopback-test:
166 type: boolean 166 type: boolean
167 description: | 167 description: |
168 Set to indicate that the port does not i 168 Set to indicate that the port does not implement loopback test mode.
169 169
170 fifo-size: 170 fifo-size:
171 $ref: /schemas/types.yaml#/definitions/uin 171 $ref: /schemas/types.yaml#/definitions/uint32
172 description: The fifo size of the UART. 172 description: The fifo size of the UART.
173 173
174 auto-flow-control: 174 auto-flow-control:
175 type: boolean 175 type: boolean
176 description: | 176 description: |
177 One way to enable automatic flow control 177 One way to enable automatic flow control support. The driver is
178 allowed to detect support for the capabi 178 allowed to detect support for the capability even without this
179 property. 179 property.
180 180
181 tx-threshold: 181 tx-threshold:
182 description: | 182 description: |
183 Specify the TX FIFO low water indication 183 Specify the TX FIFO low water indication for parts with programmable
184 TX FIFO thresholds. 184 TX FIFO thresholds.
185 185
186 overrun-throttle-ms: 186 overrun-throttle-ms:
187 description: | 187 description: |
188 How long to pause uart rx when input ove 188 How long to pause uart rx when input overrun is encountered.
189 189
190 rts-gpios: true 190 rts-gpios: true
191 cts-gpios: true 191 cts-gpios: true
192 dtr-gpios: true 192 dtr-gpios: true
193 dsr-gpios: true 193 dsr-gpios: true
194 rng-gpios: true 194 rng-gpios: true
195 dcd-gpios: true 195 dcd-gpios: true
196 196
197 aspeed,sirq-polarity-sense: 197 aspeed,sirq-polarity-sense:
198 $ref: /schemas/types.yaml#/definitions/pha 198 $ref: /schemas/types.yaml#/definitions/phandle-array
199 description: | 199 description: |
200 Phandle to aspeed,ast2500-scu compatible 200 Phandle to aspeed,ast2500-scu compatible syscon alongside register
201 offset and bit number to identify how th 201 offset and bit number to identify how the SIRQ polarity should be
202 configured. One possible data source is 202 configured. One possible data source is the LPC/eSPI mode bit. Only
203 applicable to aspeed,ast2500-vuart. 203 applicable to aspeed,ast2500-vuart.
204 deprecated: true 204 deprecated: true
205 205
206 aspeed,lpc-io-reg: 206 aspeed,lpc-io-reg:
207 $ref: /schemas/types.yaml#/definitions/uin 207 $ref: /schemas/types.yaml#/definitions/uint32-array
208 maxItems: 1 208 maxItems: 1
209 description: | 209 description: |
210 The VUART LPC address. Only applicable 210 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
211 211
212 aspeed,lpc-interrupts: 212 aspeed,lpc-interrupts:
213 $ref: /schemas/types.yaml#/definitions/uin 213 $ref: /schemas/types.yaml#/definitions/uint32-array
214 minItems: 2 214 minItems: 2
215 maxItems: 2 215 maxItems: 2
216 description: | 216 description: |
217 A 2-cell property describing the VUART S 217 A 2-cell property describing the VUART SIRQ number and SIRQ
218 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE 218 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
219 applicable to aspeed,ast2500-vuart. 219 applicable to aspeed,ast2500-vuart.
220 220
221 required: 221 required:
222 - reg 222 - reg
223 - interrupts 223 - interrupts
224 224
225 unevaluatedProperties: false 225 unevaluatedProperties: false
226 226
227 examples: 227 examples:
228 - | 228 - |
229 serial@80230000 { 229 serial@80230000 {
230 compatible = "ns8250"; 230 compatible = "ns8250";
231 reg = <0x80230000 0x100>; 231 reg = <0x80230000 0x100>;
232 interrupts = <10>; 232 interrupts = <10>;
233 reg-shift = <2>; 233 reg-shift = <2>;
234 clock-frequency = <48000000>; 234 clock-frequency = <48000000>;
235 }; 235 };
236 - | 236 - |
237 #include <dt-bindings/gpio/gpio.h> 237 #include <dt-bindings/gpio/gpio.h>
238 serial@49042000 { 238 serial@49042000 {
239 compatible = "andestech,uart16550", "n 239 compatible = "andestech,uart16550", "ns16550a";
240 reg = <0x49042000 0x400>; 240 reg = <0x49042000 0x400>;
241 interrupts = <80>; 241 interrupts = <80>;
242 clock-frequency = <48000000>; 242 clock-frequency = <48000000>;
243 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW> 243 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
244 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW> 244 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
245 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW 245 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
246 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW 246 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
247 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW 247 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
248 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW 248 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
249 }; 249 };
250 - | 250 - |
251 #include <dt-bindings/clock/aspeed-clock.h 251 #include <dt-bindings/clock/aspeed-clock.h>
252 #include <dt-bindings/interrupt-controller 252 #include <dt-bindings/interrupt-controller/irq.h>
253 serial@1e787000 { 253 serial@1e787000 {
254 compatible = "aspeed,ast2500-vuart"; 254 compatible = "aspeed,ast2500-vuart";
255 reg = <0x1e787000 0x40>; 255 reg = <0x1e787000 0x40>;
256 reg-shift = <2>; 256 reg-shift = <2>;
257 interrupts = <8>; 257 interrupts = <8>;
258 clocks = <&syscon ASPEED_CLK_APB>; 258 clocks = <&syscon ASPEED_CLK_APB>;
259 no-loopback-test; 259 no-loopback-test;
260 aspeed,lpc-io-reg = <0x3f8>; 260 aspeed,lpc-io-reg = <0x3f8>;
261 aspeed,lpc-interrupts = <4 IRQ_TYPE_LE 261 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
262 }; 262 };
263 263
264 ... 264 ...
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