1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk 1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/serial/8250 4 $id: http://devicetree.org/schemas/serial/8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: UART (Universal Asynchronous Receiver/T !! 7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
8 8
9 maintainers: 9 maintainers:
10 - devicetree@vger.kernel.org 10 - devicetree@vger.kernel.org
11 11
12 allOf: 12 allOf:
13 - $ref: serial.yaml# !! 13 - $ref: /schemas/serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-perip <<
15 - if: 14 - if:
16 anyOf: !! 15 required:
17 - required: !! 16 - aspeed,sirq-polarity-sense
18 - aspeed,lpc-io-reg <<
19 - required: <<
20 - aspeed,lpc-interrupts <<
21 - required: <<
22 - aspeed,sirq-polarity-sense <<
23 then: 17 then:
24 properties: 18 properties:
25 compatible: 19 compatible:
26 const: aspeed,ast2500-vuart 20 const: aspeed,ast2500-vuart
27 - if: 21 - if:
28 properties: 22 properties:
29 compatible: 23 compatible:
30 const: mrvl,mmp-uart 24 const: mrvl,mmp-uart
31 then: 25 then:
32 properties: 26 properties:
33 reg-shift: 27 reg-shift:
34 const: 2 28 const: 2
35 required: 29 required:
36 - reg-shift 30 - reg-shift
37 - if: 31 - if:
38 not: 32 not:
39 properties: 33 properties:
40 compatible: 34 compatible:
41 items: 35 items:
42 - enum: 36 - enum:
43 - ns8250 37 - ns8250
44 - ns16450 38 - ns16450
45 - ns16550 39 - ns16550
46 - ns16550a 40 - ns16550a
47 then: 41 then:
48 anyOf: 42 anyOf:
49 - required: [ clock-frequency ] 43 - required: [ clock-frequency ]
50 - required: [ clocks ] 44 - required: [ clocks ]
51 45
52 properties: 46 properties:
53 compatible: 47 compatible:
54 oneOf: 48 oneOf:
55 - const: ns8250 49 - const: ns8250
56 - const: ns16450 50 - const: ns16450
57 - const: ns16550 51 - const: ns16550
58 - const: ns16550a 52 - const: ns16550a
59 - const: ns16850 53 - const: ns16850
60 - const: aspeed,ast2400-vuart 54 - const: aspeed,ast2400-vuart
61 - const: aspeed,ast2500-vuart 55 - const: aspeed,ast2500-vuart
62 - const: intel,xscale-uart 56 - const: intel,xscale-uart
63 - const: mrvl,pxa-uart 57 - const: mrvl,pxa-uart
64 - const: nuvoton,wpcm450-uart <<
65 - const: nuvoton,npcm750-uart 58 - const: nuvoton,npcm750-uart
66 - const: nvidia,tegra20-uart 59 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart 60 - const: nxp,lpc3220-uart
68 - items: 61 - items:
69 - enum: 62 - enum:
70 - exar,xr16l2552 <<
71 - exar,xr16l2551 <<
72 - exar,xr16l2550 <<
73 - const: ns8250 <<
74 - items: <<
75 - enum: <<
76 - altr,16550-FIFO32 63 - altr,16550-FIFO32
77 - altr,16550-FIFO64 64 - altr,16550-FIFO64
78 - altr,16550-FIFO128 65 - altr,16550-FIFO128
79 - fsl,16550-FIFO64 66 - fsl,16550-FIFO64
80 - fsl,ns16550 67 - fsl,ns16550
81 - andestech,uart16550 68 - andestech,uart16550
82 - nxp,lpc1850-uart 69 - nxp,lpc1850-uart
83 - opencores,uart16550-rtlsvn105 70 - opencores,uart16550-rtlsvn105
84 - ti,da830-uart 71 - ti,da830-uart
85 - const: ns16550a 72 - const: ns16550a
86 - items: 73 - items:
87 - enum: 74 - enum:
88 - ns16750 75 - ns16750
89 - cavium,octeon-3860-uart 76 - cavium,octeon-3860-uart
90 - xlnx,xps-uart16550-2.00.b 77 - xlnx,xps-uart16550-2.00.b
91 - ralink,rt2880-uart 78 - ralink,rt2880-uart
92 - enum: 79 - enum:
93 - ns16550 # Deprecated, unless t 80 - ns16550 # Deprecated, unless the FIFO really is broken
94 - ns16550a 81 - ns16550a
95 - items: 82 - items:
96 - enum: 83 - enum:
97 - nuvoton,npcm845-uart <<
98 - const: nuvoton,npcm750-uart <<
99 - items: <<
100 - enum: <<
101 - ralink,mt7620a-uart 84 - ralink,mt7620a-uart
102 - ralink,rt3052-uart 85 - ralink,rt3052-uart
103 - ralink,rt3883-uart 86 - ralink,rt3883-uart
104 - const: ralink,rt2880-uart 87 - const: ralink,rt2880-uart
105 - enum: 88 - enum:
106 - ns16550 # Deprecated, unless t 89 - ns16550 # Deprecated, unless the FIFO really is broken
107 - ns16550a 90 - ns16550a
108 - items: 91 - items:
109 - enum: 92 - enum:
110 - mediatek,mt7622-btif 93 - mediatek,mt7622-btif
111 - mediatek,mt7623-btif 94 - mediatek,mt7623-btif
112 - const: mediatek,mtk-btif 95 - const: mediatek,mtk-btif
113 - items: 96 - items:
114 - const: mrvl,mmp-uart 97 - const: mrvl,mmp-uart
115 - const: intel,xscale-uart 98 - const: intel,xscale-uart
116 - items: 99 - items:
117 - enum: 100 - enum:
118 - nvidia,tegra30-uart 101 - nvidia,tegra30-uart
119 - nvidia,tegra114-uart 102 - nvidia,tegra114-uart
120 - nvidia,tegra124-uart 103 - nvidia,tegra124-uart
121 - nvidia,tegra210-uart <<
122 - nvidia,tegra186-uart 104 - nvidia,tegra186-uart
123 - nvidia,tegra194-uart 105 - nvidia,tegra194-uart
124 - nvidia,tegra234-uart !! 106 - nvidia,tegra210-uart
125 - const: nvidia,tegra20-uart 107 - const: nvidia,tegra20-uart
126 108
127 reg: 109 reg:
128 maxItems: 1 110 maxItems: 1
129 111
130 interrupts: 112 interrupts:
131 maxItems: 1 113 maxItems: 1
132 114
133 clock-frequency: true 115 clock-frequency: true
134 116
135 clocks: 117 clocks:
136 maxItems: 1 118 maxItems: 1
137 119
138 resets: 120 resets:
139 maxItems: 1 121 maxItems: 1
140 122
141 current-speed: 123 current-speed:
142 $ref: /schemas/types.yaml#/definitions/uin !! 124 $ref: /schemas/types.yaml#definitions/uint32
143 description: The current active speed of t 125 description: The current active speed of the UART.
144 126
145 reg-offset: 127 reg-offset:
146 $ref: /schemas/types.yaml#/definitions/uin <<
147 description: | 128 description: |
148 Offset to apply to the mapbase from the 129 Offset to apply to the mapbase from the start of the registers.
149 130
150 reg-shift: 131 reg-shift:
151 description: Quantity to shift the registe 132 description: Quantity to shift the register offsets by.
152 133
153 reg-io-width: 134 reg-io-width:
154 description: | 135 description: |
155 The size (in bytes) of the IO accesses t 136 The size (in bytes) of the IO accesses that should be performed on the
156 device. There are some systems that requ 137 device. There are some systems that require 32-bit accesses to the
157 UART (e.g. TI davinci). 138 UART (e.g. TI davinci).
158 139
159 used-by-rtas: 140 used-by-rtas:
160 type: boolean 141 type: boolean
161 description: | 142 description: |
162 Set to indicate that the port is in use 143 Set to indicate that the port is in use by the OpenFirmware RTAS and
163 should not be registered. 144 should not be registered.
164 145
165 no-loopback-test: 146 no-loopback-test:
166 type: boolean 147 type: boolean
167 description: | 148 description: |
168 Set to indicate that the port does not i 149 Set to indicate that the port does not implement loopback test mode.
169 150
170 fifo-size: 151 fifo-size:
171 $ref: /schemas/types.yaml#/definitions/uin !! 152 $ref: /schemas/types.yaml#definitions/uint32
172 description: The fifo size of the UART. 153 description: The fifo size of the UART.
173 154
174 auto-flow-control: 155 auto-flow-control:
175 type: boolean 156 type: boolean
176 description: | 157 description: |
177 One way to enable automatic flow control 158 One way to enable automatic flow control support. The driver is
178 allowed to detect support for the capabi 159 allowed to detect support for the capability even without this
179 property. 160 property.
180 161
181 tx-threshold: 162 tx-threshold:
>> 163 $ref: /schemas/types.yaml#definitions/uint32
182 description: | 164 description: |
183 Specify the TX FIFO low water indication 165 Specify the TX FIFO low water indication for parts with programmable
184 TX FIFO thresholds. 166 TX FIFO thresholds.
185 167
186 overrun-throttle-ms: 168 overrun-throttle-ms:
187 description: | 169 description: |
188 How long to pause uart rx when input ove 170 How long to pause uart rx when input overrun is encountered.
189 171
190 rts-gpios: true 172 rts-gpios: true
191 cts-gpios: true 173 cts-gpios: true
192 dtr-gpios: true 174 dtr-gpios: true
193 dsr-gpios: true 175 dsr-gpios: true
194 rng-gpios: true 176 rng-gpios: true
195 dcd-gpios: true 177 dcd-gpios: true
196 178
197 aspeed,sirq-polarity-sense: 179 aspeed,sirq-polarity-sense:
198 $ref: /schemas/types.yaml#/definitions/pha 180 $ref: /schemas/types.yaml#/definitions/phandle-array
199 description: | 181 description: |
200 Phandle to aspeed,ast2500-scu compatible 182 Phandle to aspeed,ast2500-scu compatible syscon alongside register
201 offset and bit number to identify how th 183 offset and bit number to identify how the SIRQ polarity should be
202 configured. One possible data source is 184 configured. One possible data source is the LPC/eSPI mode bit. Only
203 applicable to aspeed,ast2500-vuart. 185 applicable to aspeed,ast2500-vuart.
204 deprecated: true <<
205 <<
206 aspeed,lpc-io-reg: <<
207 $ref: /schemas/types.yaml#/definitions/uin <<
208 maxItems: 1 <<
209 description: | <<
210 The VUART LPC address. Only applicable <<
211 <<
212 aspeed,lpc-interrupts: <<
213 $ref: /schemas/types.yaml#/definitions/uin <<
214 minItems: 2 <<
215 maxItems: 2 <<
216 description: | <<
217 A 2-cell property describing the VUART S <<
218 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE <<
219 applicable to aspeed,ast2500-vuart. <<
220 186
221 required: 187 required:
222 - reg 188 - reg
223 - interrupts 189 - interrupts
224 190
225 unevaluatedProperties: false 191 unevaluatedProperties: false
226 192
227 examples: 193 examples:
228 - | 194 - |
229 serial@80230000 { 195 serial@80230000 {
230 compatible = "ns8250"; 196 compatible = "ns8250";
231 reg = <0x80230000 0x100>; 197 reg = <0x80230000 0x100>;
232 interrupts = <10>; 198 interrupts = <10>;
233 reg-shift = <2>; 199 reg-shift = <2>;
234 clock-frequency = <48000000>; 200 clock-frequency = <48000000>;
235 }; 201 };
236 - | 202 - |
237 #include <dt-bindings/gpio/gpio.h> 203 #include <dt-bindings/gpio/gpio.h>
238 serial@49042000 { 204 serial@49042000 {
239 compatible = "andestech,uart16550", "n 205 compatible = "andestech,uart16550", "ns16550a";
240 reg = <0x49042000 0x400>; 206 reg = <0x49042000 0x400>;
241 interrupts = <80>; 207 interrupts = <80>;
242 clock-frequency = <48000000>; 208 clock-frequency = <48000000>;
243 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW> 209 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
244 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW> 210 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
245 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW 211 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
246 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW 212 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
247 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW 213 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
248 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW 214 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
249 }; 215 };
250 - | 216 - |
251 #include <dt-bindings/clock/aspeed-clock.h 217 #include <dt-bindings/clock/aspeed-clock.h>
252 #include <dt-bindings/interrupt-controller <<
253 serial@1e787000 { 218 serial@1e787000 {
254 compatible = "aspeed,ast2500-vuart"; 219 compatible = "aspeed,ast2500-vuart";
255 reg = <0x1e787000 0x40>; 220 reg = <0x1e787000 0x40>;
256 reg-shift = <2>; 221 reg-shift = <2>;
257 interrupts = <8>; 222 interrupts = <8>;
258 clocks = <&syscon ASPEED_CLK_APB>; 223 clocks = <&syscon ASPEED_CLK_APB>;
259 no-loopback-test; 224 no-loopback-test;
260 aspeed,lpc-io-reg = <0x3f8>; !! 225 aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
261 aspeed,lpc-interrupts = <4 IRQ_TYPE_LE <<
262 }; 226 };
263 227
264 ... 228 ...
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