1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/serial/rene !! 4 $id: "http://devicetree.org/schemas/serial/renesas,hscif.yaml#"
5 $schema: http://devicetree.org/meta-schemas/co !! 5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
6 6
7 title: Renesas High Speed Serial Communication 7 title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF)
8 8
9 maintainers: 9 maintainers:
10 - Geert Uytterhoeven <geert+renesas@glider.be 10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 11
12 allOf: 12 allOf:
13 - $ref: serial.yaml# 13 - $ref: serial.yaml#
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 oneOf: 17 oneOf:
18 - items: 18 - items:
19 - enum: 19 - enum:
20 - renesas,hscif-r8a7778 # R 20 - renesas,hscif-r8a7778 # R-Car M1
21 - renesas,hscif-r8a7779 # R 21 - renesas,hscif-r8a7779 # R-Car H1
22 - const: renesas,rcar-gen1-hscif # R 22 - const: renesas,rcar-gen1-hscif # R-Car Gen1
23 - const: renesas,hscif # g 23 - const: renesas,hscif # generic HSCIF compatible UART
24 24
25 - items: 25 - items:
26 - enum: 26 - enum:
27 - renesas,hscif-r8a7742 # R 27 - renesas,hscif-r8a7742 # RZ/G1H
28 - renesas,hscif-r8a7743 # R 28 - renesas,hscif-r8a7743 # RZ/G1M
29 - renesas,hscif-r8a7744 # R 29 - renesas,hscif-r8a7744 # RZ/G1N
30 - renesas,hscif-r8a7745 # R 30 - renesas,hscif-r8a7745 # RZ/G1E
31 - renesas,hscif-r8a77470 # R 31 - renesas,hscif-r8a77470 # RZ/G1C
32 - renesas,hscif-r8a7790 # R 32 - renesas,hscif-r8a7790 # R-Car H2
33 - renesas,hscif-r8a7791 # R 33 - renesas,hscif-r8a7791 # R-Car M2-W
34 - renesas,hscif-r8a7792 # R 34 - renesas,hscif-r8a7792 # R-Car V2H
35 - renesas,hscif-r8a7793 # R 35 - renesas,hscif-r8a7793 # R-Car M2-N
36 - renesas,hscif-r8a7794 # R 36 - renesas,hscif-r8a7794 # R-Car E2
37 - const: renesas,rcar-gen2-hscif # R 37 - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1
38 - const: renesas,hscif # g 38 - const: renesas,hscif # generic HSCIF compatible UART
39 39
40 - items: 40 - items:
41 - enum: 41 - enum:
42 - renesas,hscif-r8a774a1 # R 42 - renesas,hscif-r8a774a1 # RZ/G2M
43 - renesas,hscif-r8a774b1 # R 43 - renesas,hscif-r8a774b1 # RZ/G2N
44 - renesas,hscif-r8a774c0 # R 44 - renesas,hscif-r8a774c0 # RZ/G2E
45 - renesas,hscif-r8a774e1 # R 45 - renesas,hscif-r8a774e1 # RZ/G2H
46 - renesas,hscif-r8a7795 # R 46 - renesas,hscif-r8a7795 # R-Car H3
47 - renesas,hscif-r8a7796 # R 47 - renesas,hscif-r8a7796 # R-Car M3-W
48 - renesas,hscif-r8a77961 # R 48 - renesas,hscif-r8a77961 # R-Car M3-W+
49 - renesas,hscif-r8a77965 # R 49 - renesas,hscif-r8a77965 # R-Car M3-N
50 - renesas,hscif-r8a77970 # R 50 - renesas,hscif-r8a77970 # R-Car V3M
51 - renesas,hscif-r8a77980 # R 51 - renesas,hscif-r8a77980 # R-Car V3H
52 - renesas,hscif-r8a77990 # R 52 - renesas,hscif-r8a77990 # R-Car E3
53 - renesas,hscif-r8a77995 # R 53 - renesas,hscif-r8a77995 # R-Car D3
54 - const: renesas,rcar-gen3-hscif # R <<
55 - const: renesas,hscif # g <<
56 <<
57 - items: <<
58 - enum: <<
59 - renesas,hscif-r8a779a0 # R 54 - renesas,hscif-r8a779a0 # R-Car V3U
60 - renesas,hscif-r8a779f0 # R !! 55 - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2
61 - renesas,hscif-r8a779g0 # R <<
62 - renesas,hscif-r8a779h0 # R <<
63 - const: renesas,rcar-gen4-hscif # R <<
64 - const: renesas,hscif # g 56 - const: renesas,hscif # generic HSCIF compatible UART
65 57
66 reg: 58 reg:
67 maxItems: 1 59 maxItems: 1
68 60
69 interrupts: 61 interrupts:
70 maxItems: 1 62 maxItems: 1
71 63
72 clocks: 64 clocks:
73 minItems: 1 65 minItems: 1
74 maxItems: 4 66 maxItems: 4
75 67
76 clock-names: 68 clock-names:
77 minItems: 1 69 minItems: 1
78 maxItems: 4 70 maxItems: 4
79 items: 71 items:
80 enum: 72 enum:
81 - fck # UART functional clock 73 - fck # UART functional clock
82 - hsck # optional external clock input 74 - hsck # optional external clock input
83 - brg_int # optional internal clock so 75 - brg_int # optional internal clock source for BRG frequency divider
84 - scif_clk # optional external clock s 76 - scif_clk # optional external clock source for BRG frequency divider
85 77
86 power-domains: 78 power-domains:
87 maxItems: 1 79 maxItems: 1
88 80
89 resets: 81 resets:
90 maxItems: 1 82 maxItems: 1
91 83
92 dmas: 84 dmas:
93 minItems: 2 85 minItems: 2
94 maxItems: 4 86 maxItems: 4
95 description: 87 description:
96 Must contain a list of pairs of referenc 88 Must contain a list of pairs of references to DMA specifiers, one for
97 transmission, and one for reception. 89 transmission, and one for reception.
98 90
99 dma-names: 91 dma-names:
100 minItems: 2 92 minItems: 2
101 maxItems: 4 93 maxItems: 4
102 items: 94 items:
103 enum: 95 enum:
104 - tx 96 - tx
105 - rx 97 - rx
106 98
107 required: 99 required:
108 - compatible 100 - compatible
109 - reg 101 - reg
110 - interrupts 102 - interrupts
111 - clocks 103 - clocks
112 - clock-names 104 - clock-names
113 - power-domains 105 - power-domains
114 106
>> 107 unevaluatedProperties: false
>> 108
115 if: 109 if:
116 properties: 110 properties:
117 compatible: 111 compatible:
118 contains: 112 contains:
119 enum: 113 enum:
120 - renesas,rcar-gen2-hscif 114 - renesas,rcar-gen2-hscif
121 - renesas,rcar-gen3-hscif 115 - renesas,rcar-gen3-hscif
122 - renesas,rcar-gen4-hscif <<
123 then: 116 then:
124 required: 117 required:
125 - resets 118 - resets
126 119
127 unevaluatedProperties: false <<
128 <<
129 examples: 120 examples:
130 - | 121 - |
131 #include <dt-bindings/clock/r8a7795-cpg-ms 122 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
132 #include <dt-bindings/interrupt-controller 123 #include <dt-bindings/interrupt-controller/arm-gic.h>
133 #include <dt-bindings/power/r8a7795-sysc.h 124 #include <dt-bindings/power/r8a7795-sysc.h>
134 aliases { 125 aliases {
135 serial1 = &hscif1; !! 126 serial1 = &hscif1;
136 }; 127 };
137 128
138 hscif1: serial@e6550000 { 129 hscif1: serial@e6550000 {
139 compatible = "renesas,hscif-r8a7795", !! 130 compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif",
140 "renesas,hscif"; !! 131 "renesas,hscif";
141 reg = <0xe6550000 96>; !! 132 reg = <0xe6550000 96>;
142 interrupts = <GIC_SPI 155 IRQ_TYPE_LEV !! 133 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&cpg CPG_MOD 519>, <&cpg CPG !! 134 clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
144 <&scif_clk>; !! 135 <&scif_clk>;
145 clock-names = "fck", "brg_int", "scif_ !! 136 clock-names = "fck", "brg_int", "scif_clk";
146 dmas = <&dmac1 0x33>, <&dmac1 0x32>, < !! 137 dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>;
147 dma-names = "tx", "rx", "tx", "rx"; !! 138 dma-names = "tx", "rx", "tx", "rx";
148 power-domains = <&sysc R8A7795_PD_ALWA !! 139 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
149 resets = <&cpg 519>; !! 140 resets = <&cpg 519>;
150 uart-has-rtscts; !! 141 uart-has-rtscts;
151 }; 142 };
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