1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl 4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NXP i.MX8MP Media Block Control 7 title: NXP i.MX8MP Media Block Control
8 8
9 maintainers: 9 maintainers:
10 - Paul Elder <paul.elder@ideasonboard.com> 10 - Paul Elder <paul.elder@ideasonboard.com>
11 11
12 description: 12 description:
13 The i.MX8MP Media Block Control (MEDIA BLK_C 13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
14 providing access to the NoC and ensuring pro 14 providing access to the NoC and ensuring proper power sequencing of the
15 peripherals within the MEDIAMIX domain. 15 peripherals within the MEDIAMIX domain.
16 16
17 properties: 17 properties:
18 compatible: 18 compatible:
19 items: 19 items:
20 - const: fsl,imx8mp-media-blk-ctrl 20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon 21 - const: syscon
22 22
23 reg: 23 reg:
24 maxItems: 1 24 maxItems: 1
25 25
26 '#address-cells': 26 '#address-cells':
27 const: 1 27 const: 1
28 28
29 '#size-cells': 29 '#size-cells':
30 const: 1 30 const: 1
31 31
32 '#power-domain-cells': 32 '#power-domain-cells':
33 const: 1 33 const: 1
34 34
35 power-domains: 35 power-domains:
36 maxItems: 10 36 maxItems: 10
37 37
38 power-domain-names: 38 power-domain-names:
39 items: 39 items:
40 - const: bus 40 - const: bus
41 - const: mipi-dsi1 41 - const: mipi-dsi1
42 - const: mipi-csi1 42 - const: mipi-csi1
43 - const: lcdif1 43 - const: lcdif1
44 - const: isi 44 - const: isi
45 - const: mipi-csi2 45 - const: mipi-csi2
46 - const: lcdif2 46 - const: lcdif2
47 - const: isp 47 - const: isp
48 - const: dwe 48 - const: dwe
49 - const: mipi-dsi2 49 - const: mipi-dsi2
50 50
51 clocks: 51 clocks:
52 items: 52 items:
53 - description: The APB clock 53 - description: The APB clock
54 - description: The AXI clock 54 - description: The AXI clock
55 - description: The pixel clock for the f 55 - description: The pixel clock for the first CSI2 receiver (aclk)
56 - description: The pixel clock for the s 56 - description: The pixel clock for the second CSI2 receiver (aclk)
57 - description: The pixel clock for the f 57 - description: The pixel clock for the first LCDIF (pix_clk)
58 - description: The pixel clock for the s 58 - description: The pixel clock for the second LCDIF (pix_clk)
59 - description: The core clock for the IS 59 - description: The core clock for the ISP (clk)
60 - description: The MIPI-PHY reference cl 60 - description: The MIPI-PHY reference clock used by DSI
61 61
62 clock-names: 62 clock-names:
63 items: 63 items:
64 - const: apb 64 - const: apb
65 - const: axi 65 - const: axi
66 - const: cam1 66 - const: cam1
67 - const: cam2 67 - const: cam2
68 - const: disp1 68 - const: disp1
69 - const: disp2 69 - const: disp2
70 - const: isp 70 - const: isp
71 - const: phy 71 - const: phy
72 72
73 interconnects: 73 interconnects:
74 maxItems: 8 74 maxItems: 8
75 75
76 interconnect-names: 76 interconnect-names:
77 items: 77 items:
78 - const: lcdif-rd 78 - const: lcdif-rd
79 - const: lcdif-wr 79 - const: lcdif-wr
80 - const: isi0 80 - const: isi0
81 - const: isi1 81 - const: isi1
82 - const: isi2 82 - const: isi2
83 - const: isp0 83 - const: isp0
84 - const: isp1 84 - const: isp1
85 - const: dwe 85 - const: dwe
86 86
87 bridge@5c: 87 bridge@5c:
88 type: object 88 type: object
89 $ref: /schemas/display/bridge/fsl,ldb.yaml 89 $ref: /schemas/display/bridge/fsl,ldb.yaml#
90 unevaluatedProperties: false 90 unevaluatedProperties: false
91 91
92 required: 92 required:
93 - compatible 93 - compatible
94 - reg 94 - reg
95 - '#address-cells' 95 - '#address-cells'
96 - '#size-cells' 96 - '#size-cells'
97 - '#power-domain-cells' 97 - '#power-domain-cells'
98 - power-domains 98 - power-domains
99 - power-domain-names 99 - power-domain-names
100 - clocks 100 - clocks
101 - clock-names 101 - clock-names
102 102
103 additionalProperties: false 103 additionalProperties: false
104 104
105 examples: 105 examples:
106 - | 106 - |
107 #include <dt-bindings/clock/imx8mp-clock.h 107 #include <dt-bindings/clock/imx8mp-clock.h>
108 #include <dt-bindings/power/imx8mp-power.h 108 #include <dt-bindings/power/imx8mp-power.h>
109 109
110 blk-ctrl@32ec0000 { 110 blk-ctrl@32ec0000 {
111 compatible = "fsl,imx8mp-media-blk-ctr 111 compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
112 reg = <0x32ec0000 0x138>; 112 reg = <0x32ec0000 0x138>;
113 power-domains = <&mediamix_pd>, <&mipi 113 power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
114 <&mediamix_pd>, <&medi 114 <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
115 <&mediamix_pd>, <&ispd 115 <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
116 <&mipi_phy2_pd>; 116 <&mipi_phy2_pd>;
117 power-domain-names = "bus", "mipi-dsi1 117 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
118 "mipi-csi2", "lcd 118 "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2";
119 clocks = <&clk IMX8MP_CLK_MEDIA_APB_RO 119 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
120 <&clk IMX8MP_CLK_MEDIA_AXI_RO 120 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
121 <&clk IMX8MP_CLK_MEDIA_CAM1_P 121 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
122 <&clk IMX8MP_CLK_MEDIA_CAM2_P 122 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
123 <&clk IMX8MP_CLK_MEDIA_DISP1_ 123 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
124 <&clk IMX8MP_CLK_MEDIA_DISP2_ 124 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
125 <&clk IMX8MP_CLK_MEDIA_ISP_RO 125 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
126 <&clk IMX8MP_CLK_MEDIA_MIPI_P 126 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
127 clock-names = "apb", "axi", "cam1", "c 127 clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
128 "isp", "phy"; 128 "isp", "phy";
129 #power-domain-cells = <1>; 129 #power-domain-cells = <1>;
130 #address-cells = <1>; 130 #address-cells = <1>;
131 #size-cells = <1>; 131 #size-cells = <1>;
132 132
133 bridge@5c { 133 bridge@5c {
134 compatible = "fsl,imx8mp-ldb"; 134 compatible = "fsl,imx8mp-ldb";
135 reg = <0x5c 0x4>, <0x128 0x4>; 135 reg = <0x5c 0x4>, <0x128 0x4>;
136 reg-names = "ldb", "lvds"; 136 reg-names = "ldb", "lvds";
137 clocks = <&clk IMX8MP_CLK_MEDIA_LD 137 clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
138 clock-names = "ldb"; 138 clock-names = "ldb";
139 139
140 ports { 140 ports {
141 #address-cells = <1>; 141 #address-cells = <1>;
142 #size-cells = <0>; 142 #size-cells = <0>;
143 143
144 port@0 { 144 port@0 {
145 reg = <0>; 145 reg = <0>;
146 146
147 ldb_from_lcdif2: endpoint 147 ldb_from_lcdif2: endpoint {
148 remote-endpoint = <&lc 148 remote-endpoint = <&lcdif2_to_ldb>;
149 }; 149 };
150 }; 150 };
151 151
152 port@1 { 152 port@1 {
153 reg = <1>; 153 reg = <1>;
154 154
155 ldb_lvds_ch0: endpoint { 155 ldb_lvds_ch0: endpoint {
156 remote-endpoint = <&ld 156 remote-endpoint = <&ldb_to_lvdsx4panel>;
157 }; 157 };
158 }; 158 };
159 159
160 port@2 { 160 port@2 {
161 reg = <2>; 161 reg = <2>;
162 162
163 ldb_lvds_ch1: endpoint { 163 ldb_lvds_ch1: endpoint {
164 }; 164 };
165 }; 165 };
166 }; 166 };
167 }; 167 };
168 }; 168 };
169 ... 169 ...
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