1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qc 4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: GENI Serial Engine QUP Wrapper Controll 7 title: GENI Serial Engine QUP Wrapper Controller
8 8
9 maintainers: 9 maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org 10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 11
12 description: | 12 description: |
13 Generic Interface (GENI) based Qualcomm Unive 13 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
14 is a programmable module for supporting a wid 14 is a programmable module for supporting a wide range of serial interfaces
15 like UART, SPI, I2C, I3C, etc. A single QUP m 15 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
16 Interfaces, using its internal Serial Engines 16 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
17 Wrapper controller is modeled as a node with 17 Wrapper controller is modeled as a node with zero or more child nodes each
18 representing a serial engine. 18 representing a serial engine.
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 enum: 22 enum:
23 - qcom,geni-se-qup 23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub 24 - qcom,geni-se-i2c-master-hub
25 25
26 reg: 26 reg:
27 description: QUP wrapper common register a 27 description: QUP wrapper common register address and length.
28 maxItems: 1 28 maxItems: 1
29 29
30 clock-names: 30 clock-names:
31 minItems: 1 31 minItems: 1
32 maxItems: 2 32 maxItems: 2
33 33
34 clocks: 34 clocks:
35 minItems: 1 35 minItems: 1
36 maxItems: 2 36 maxItems: 2
37 37
38 "#address-cells": 38 "#address-cells":
39 const: 2 39 const: 2
40 40
41 "#size-cells": 41 "#size-cells":
42 const: 2 42 const: 2
43 43
44 ranges: true 44 ranges: true
45 45
46 interconnects: 46 interconnects:
47 maxItems: 1 47 maxItems: 1
48 48
49 interconnect-names: 49 interconnect-names:
50 const: qup-core 50 const: qup-core
51 51
52 iommus: 52 iommus:
53 maxItems: 1 53 maxItems: 1
54 54
55 dma-coherent: true 55 dma-coherent: true
56 56
57 required: 57 required:
58 - compatible 58 - compatible
59 - reg 59 - reg
60 - clock-names 60 - clock-names
61 - clocks 61 - clocks
62 - "#address-cells" 62 - "#address-cells"
63 - "#size-cells" 63 - "#size-cells"
64 - ranges 64 - ranges
65 65
66 patternProperties: 66 patternProperties:
67 "spi@[0-9a-f]+$": 67 "spi@[0-9a-f]+$":
68 type: object 68 type: object
69 description: GENI serial engine based SPI 69 description: GENI serial engine based SPI controller. SPI in master mode
70 supports up to 50MHz, up to f 70 supports up to 50MHz, up to four chip selects, programmable
71 data path from 4 bits to 32 b 71 data path from 4 bits to 32 bits and numerous protocol
72 variants. 72 variants.
73 $ref: /schemas/spi/qcom,spi-geni-qcom.yaml 73 $ref: /schemas/spi/qcom,spi-geni-qcom.yaml#
74 74
75 "i2c@[0-9a-f]+$": 75 "i2c@[0-9a-f]+$":
76 type: object 76 type: object
77 description: GENI serial engine based I2C 77 description: GENI serial engine based I2C controller.
78 $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml 78 $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#
79 79
80 "serial@[0-9a-f]+$": 80 "serial@[0-9a-f]+$":
81 type: object 81 type: object
82 description: GENI Serial Engine based UART 82 description: GENI Serial Engine based UART Controller.
83 $ref: /schemas/serial/qcom,serial-geni-qco 83 $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
84 84
85 allOf: 85 allOf:
86 - if: 86 - if:
87 properties: 87 properties:
88 compatible: 88 compatible:
89 contains: 89 contains:
90 const: qcom,geni-se-i2c-master-hub 90 const: qcom,geni-se-i2c-master-hub
91 then: 91 then:
92 properties: 92 properties:
93 clock-names: 93 clock-names:
94 items: 94 items:
95 - const: s-ahb 95 - const: s-ahb
96 96
97 clocks: 97 clocks:
98 items: 98 items:
99 - description: Slave AHB Clock 99 - description: Slave AHB Clock
100 100
101 iommus: false 101 iommus: false
102 102
103 patternProperties: 103 patternProperties:
104 "spi@[0-9a-f]+$": false 104 "spi@[0-9a-f]+$": false
105 "serial@[0-9a-f]+$": false 105 "serial@[0-9a-f]+$": false
106 else: 106 else:
107 properties: 107 properties:
108 clock-names: 108 clock-names:
109 items: 109 items:
110 - const: m-ahb 110 - const: m-ahb
111 - const: s-ahb 111 - const: s-ahb
112 112
113 clocks: 113 clocks:
114 items: 114 items:
115 - description: Master AHB Clock 115 - description: Master AHB Clock
116 - description: Slave AHB Clock 116 - description: Slave AHB Clock
117 117
118 additionalProperties: false 118 additionalProperties: false
119 119
120 examples: 120 examples:
121 - | 121 - |
122 #include <dt-bindings/clock/qcom,gcc-sdm84 122 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
123 #include <dt-bindings/interrupt-controller 123 #include <dt-bindings/interrupt-controller/arm-gic.h>
124 124
125 soc { 125 soc {
126 #address-cells = <2>; 126 #address-cells = <2>;
127 #size-cells = <2>; 127 #size-cells = <2>;
128 128
129 geniqup@8c0000 { 129 geniqup@8c0000 {
130 compatible = "qcom,geni-se-qup"; 130 compatible = "qcom,geni-se-qup";
131 reg = <0 0x008c0000 0 0x6000>; 131 reg = <0 0x008c0000 0 0x6000>;
132 clock-names = "m-ahb", "s-ahb"; 132 clock-names = "m-ahb", "s-ahb";
133 clocks = <&gcc GCC_QUPV3_WRAP_0_M_ 133 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
134 <&gcc GCC_QUPV3_WRAP_0_S_AHB_C 134 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
135 #address-cells = <2>; 135 #address-cells = <2>;
136 #size-cells = <2>; 136 #size-cells = <2>;
137 ranges; 137 ranges;
138 138
139 i2c0: i2c@a94000 { 139 i2c0: i2c@a94000 {
140 compatible = "qcom,geni-i2c"; 140 compatible = "qcom,geni-i2c";
141 reg = <0 0xa94000 0 0x4000>; 141 reg = <0 0xa94000 0 0x4000>;
142 interrupts = <GIC_SPI 358 IRQ_ 142 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
143 clock-names = "se"; 143 clock-names = "se";
144 clocks = <&gcc GCC_QUPV3_WRAP0 144 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
145 pinctrl-names = "default", "sl 145 pinctrl-names = "default", "sleep";
146 pinctrl-0 = <&qup_1_i2c_5_acti 146 pinctrl-0 = <&qup_1_i2c_5_active>;
147 pinctrl-1 = <&qup_1_i2c_5_slee 147 pinctrl-1 = <&qup_1_i2c_5_sleep>;
148 #address-cells = <1>; 148 #address-cells = <1>;
149 #size-cells = <0>; 149 #size-cells = <0>;
150 }; 150 };
151 151
152 uart0: serial@a88000 { 152 uart0: serial@a88000 {
153 compatible = "qcom,geni-uart"; 153 compatible = "qcom,geni-uart";
154 reg = <0 0xa88000 0 0x7000>; 154 reg = <0 0xa88000 0 0x7000>;
155 interrupts = <GIC_SPI 355 IRQ_ 155 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
156 clock-names = "se"; 156 clock-names = "se";
157 clocks = <&gcc GCC_QUPV3_WRAP0 157 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
158 pinctrl-names = "default", "sl 158 pinctrl-names = "default", "sleep";
159 pinctrl-0 = <&qup_1_uart_3_act 159 pinctrl-0 = <&qup_1_uart_3_active>;
160 pinctrl-1 = <&qup_1_uart_3_sle 160 pinctrl-1 = <&qup_1_uart_3_sleep>;
161 }; 161 };
162 }; 162 };
163 }; 163 };
164 164
165 ... 165 ...
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