1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorpo 2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/soc/ti/k3-r !! 5 $id: "http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml#"
6 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 7
8 title: Texas Instruments K3 NavigatorSS Ring A 8 title: Texas Instruments K3 NavigatorSS Ring Accelerator
9 9
10 maintainers: 10 maintainers:
11 - Santosh Shilimkar <ssantosh@kernel.org> 11 - Santosh Shilimkar <ssantosh@kernel.org>
12 - Grygorii Strashko <grygorii.strashko@ti.com 12 - Grygorii Strashko <grygorii.strashko@ti.com>
13 13
14 description: | 14 description: |
15 The Ring Accelerator (RA) is a machine which 15 The Ring Accelerator (RA) is a machine which converts read/write accesses
16 from/to a constant address into correspondin 16 from/to a constant address into corresponding read/write accesses from/to a
17 circular data structure in memory. The RA el 17 circular data structure in memory. The RA eliminates the need for each DMA
18 controller which needs to access ring elemen 18 controller which needs to access ring elements from having to know the current
19 state of the ring (base address, current off 19 state of the ring (base address, current offset). The DMA controller
20 performs a read or write access to a specifi 20 performs a read or write access to a specific address range (which maps to the
21 source interface on the RA) and the RA repla 21 source interface on the RA) and the RA replaces the address for the transaction
22 with a new address which corresponds to the 22 with a new address which corresponds to the head or tail element of the ring
23 (head for reads, tail for writes). 23 (head for reads, tail for writes).
24 24
25 The Ring Accelerator is a hardware module th 25 The Ring Accelerator is a hardware module that is responsible for accelerating
26 management of the packet queues. The K3 SoCs 26 management of the packet queues. The K3 SoCs can have more than one RA instances
27 27
28 allOf: <<
29 - $ref: /schemas/arm/keystone/ti,k3-sci-comm <<
30 <<
31 properties: 28 properties:
32 compatible: 29 compatible:
33 items: 30 items:
34 - const: ti,am654-navss-ringacc 31 - const: ti,am654-navss-ringacc
35 32
36 reg: 33 reg:
37 minItems: 4 <<
38 items: 34 items:
39 - description: real time registers regio 35 - description: real time registers regions
40 - description: fifos registers regions 36 - description: fifos registers regions
41 - description: proxy gcfg registers regi 37 - description: proxy gcfg registers regions
42 - description: proxy target registers re 38 - description: proxy target registers regions
43 - description: configuration registers r <<
44 39
45 reg-names: 40 reg-names:
46 minItems: 4 <<
47 items: 41 items:
48 - const: rt 42 - const: rt
49 - const: fifos 43 - const: fifos
50 - const: proxy_gcfg 44 - const: proxy_gcfg
51 - const: proxy_target 45 - const: proxy_target
52 - const: cfg <<
53 46
54 msi-parent: true 47 msi-parent: true
55 48
56 ti,num-rings: 49 ti,num-rings:
57 $ref: /schemas/types.yaml#/definitions/uin 50 $ref: /schemas/types.yaml#/definitions/uint32
58 description: Number of rings supported by 51 description: Number of rings supported by RA
59 52
60 ti,sci-rm-range-gp-rings: 53 ti,sci-rm-range-gp-rings:
61 $ref: /schemas/types.yaml#/definitions/uin 54 $ref: /schemas/types.yaml#/definitions/uint32
62 description: TI-SCI RM subtype for GP ring 55 description: TI-SCI RM subtype for GP ring range
63 56
>> 57 ti,sci:
>> 58 $ref: /schemas/types.yaml#/definitions/phandle-array
>> 59 description: phandle on TI-SCI compatible System controller node
>> 60
>> 61 ti,sci-dev-id:
>> 62 $ref: /schemas/types.yaml#/definitions/uint32
>> 63 description: TI-SCI device id of the ring accelerator
>> 64
64 required: 65 required:
65 - compatible 66 - compatible
66 - reg 67 - reg
67 - reg-names 68 - reg-names
68 - msi-parent 69 - msi-parent
69 - ti,num-rings 70 - ti,num-rings
70 - ti,sci-rm-range-gp-rings 71 - ti,sci-rm-range-gp-rings
71 - ti,sci 72 - ti,sci
72 - ti,sci-dev-id 73 - ti,sci-dev-id
73 74
74 unevaluatedProperties: false !! 75 additionalProperties: false
75 76
76 examples: 77 examples:
77 - | 78 - |
78 bus { 79 bus {
79 #address-cells = <2>; 80 #address-cells = <2>;
80 #size-cells = <2>; 81 #size-cells = <2>;
81 82
82 ringacc: ringacc@3c000000 { 83 ringacc: ringacc@3c000000 {
83 compatible = "ti,am654-navss-ringa 84 compatible = "ti,am654-navss-ringacc";
84 reg = <0x0 0x3c000000 0x0 0x400000 85 reg = <0x0 0x3c000000 0x0 0x400000>,
85 <0x0 0x38000000 0x0 0x400000 86 <0x0 0x38000000 0x0 0x400000>,
86 <0x0 0x31120000 0x0 0x100>, 87 <0x0 0x31120000 0x0 0x100>,
87 <0x0 0x33000000 0x0 0x40000> !! 88 <0x0 0x33000000 0x0 0x40000>;
88 <0x0 0x31080000 0x0 0x40000> !! 89 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
89 reg-names = "rt", "fifos", " <<
90 ti,num-rings = <818>; 90 ti,num-rings = <818>;
91 ti,sci-rm-range-gp-rings = <0x2>; 91 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
92 ti,sci = <&dmsc>; 92 ti,sci = <&dmsc>;
93 ti,sci-dev-id = <187>; 93 ti,sci-dev-id = <187>;
94 msi-parent = <&inta_main_udmass>; 94 msi-parent = <&inta_main_udmass>;
95 }; 95 };
96 }; 96 };
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