1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/soc/ti/ti,p 4 $id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: |+ 7 title: |+
8 TI Programmable Real-Time Unit and Industria 8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
9 9
10 maintainers: 10 maintainers:
11 - Suman Anna <s-anna@ti.com> 11 - Suman Anna <s-anna@ti.com>
12 12
13 description: |+ 13 description: |+
14 14
15 The Programmable Real-Time Unit and Industri 15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on variou 16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUS 17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs 18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
19 instruction RAMs, some internal peripheral m 19 instruction RAMs, some internal peripheral modules to facilitate industrial
20 communication, and an interrupt controller. 20 communication, and an interrupt controller.
21 21
22 The programmable nature of the PRUs provide 22 The programmable nature of the PRUs provide flexibility to implement custom
23 peripheral interfaces, fast real-time respon 23 peripheral interfaces, fast real-time responses, or specialized data handling.
24 The common peripheral modules include the fo 24 The common peripheral modules include the following,
25 - an Ethernet MII_RT module with two MII p 25 - an Ethernet MII_RT module with two MII ports
26 - an MDIO port to control external Etherne 26 - an MDIO port to control external Ethernet PHYs
27 - an Industrial Ethernet Peripheral (IEP) 27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
28 Ethernet functions 28 Ethernet functions
29 - an Enhanced Capture Module (eCAP) 29 - an Enhanced Capture Module (eCAP)
30 - an Industrial Ethernet Timer with 7/9 ca 30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events
31 - a 16550-compatible UART to support PROFI 31 - a 16550-compatible UART to support PROFIBUS
32 - Enhanced GPIO with async capture and ser 32 - Enhanced GPIO with async capture and serial support
33 33
34 A PRU-ICSS subsystem can have up to three sh 34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
35 acts on a primary Data RAM (there are usuall 35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36 0x0, but also has access to a secondary Data 36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data R 37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
38 by both the PRU cores. The Interrupt Control 38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39 common to both the PRU cores. Each PRU core 39 common to both the PRU cores. Each PRU core also has a private instruction
40 RAM, and specific register spaces for Contro 40 RAM, and specific register spaces for Control and Debug functionalities.
41 41
42 Various sub-modules within a PRU-ICSS subsys 42 Various sub-modules within a PRU-ICSS subsystem are represented as individual
43 nodes and are defined using a parent-child h 43 nodes and are defined using a parent-child hierarchy depending on their
44 integration within the IP and the SoC. These 44 integration within the IP and the SoC. These nodes are described in the
45 following sections. 45 following sections.
46 46
47 47
48 PRU-ICSS Node 48 PRU-ICSS Node
49 ============== 49 ==============
50 Each PRU-ICSS instance is represented as its 50 Each PRU-ICSS instance is represented as its own node with the individual PRU
51 processor cores, the memories node, an INTC 51 processor cores, the memories node, an INTC node and an MDIO node represented
52 as child nodes within this PRUSS node. This 52 as child nodes within this PRUSS node. This node shall be a child of the
53 corresponding interconnect bus nodes or targ 53 corresponding interconnect bus nodes or target-module nodes.
54 54
55 See ../../mfd/syscon.yaml for generic SysCon 55 See ../../mfd/syscon.yaml for generic SysCon binding details.
56 56
57 57
58 properties: 58 properties:
59 $nodename: 59 $nodename:
60 pattern: "^(pruss|icssg)@[0-9a-f]+$" 60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
61 61
62 compatible: 62 compatible:
63 enum: 63 enum:
64 - ti,am3356-pruss # for AM335x SoC fami 64 - ti,am3356-pruss # for AM335x SoC family
65 - ti,am4376-pruss0 # for AM437x SoC fami 65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
66 - ti,am4376-pruss1 # for AM437x SoC fami 66 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
67 - ti,am5728-pruss # for AM57xx SoC fami 67 - ti,am5728-pruss # for AM57xx SoC family
68 - ti,am625-pruss # for K3 AM62x SoC fa 68 - ti,am625-pruss # for K3 AM62x SoC family
69 - ti,am642-icssg # for K3 AM64x SoC fa 69 - ti,am642-icssg # for K3 AM64x SoC family
70 - ti,am654-icssg # for K3 AM65x SoC fa 70 - ti,am654-icssg # for K3 AM65x SoC family
71 - ti,j721e-icssg # for K3 J721E SoC fa 71 - ti,j721e-icssg # for K3 J721E SoC family
72 - ti,k2g-pruss # for 66AK2G SoC fami 72 - ti,k2g-pruss # for 66AK2G SoC family
73 73
74 reg: 74 reg:
75 maxItems: 1 75 maxItems: 1
76 76
77 "#address-cells": 77 "#address-cells":
78 const: 1 78 const: 1
79 79
80 "#size-cells": 80 "#size-cells":
81 const: 1 81 const: 1
82 82
83 ranges: 83 ranges:
84 maxItems: 1 84 maxItems: 1
85 85
86 dma-ranges: 86 dma-ranges:
87 maxItems: 1 87 maxItems: 1
88 88
89 dma-coherent: true 89 dma-coherent: true
90 90
91 power-domains: 91 power-domains:
92 description: | 92 description: |
93 This property is as per sci-pm-domain.tx 93 This property is as per sci-pm-domain.txt.
94 94
95 patternProperties: 95 patternProperties:
96 96
97 memories@[a-f0-9]+$: 97 memories@[a-f0-9]+$:
98 description: | 98 description: |
99 The various Data RAMs within a single PR 99 The various Data RAMs within a single PRU-ICSS unit are represented as a
100 single node with the name 'memories'. 100 single node with the name 'memories'.
101 101
102 type: object 102 type: object
103 103
104 properties: 104 properties:
105 reg: 105 reg:
106 minItems: 2 # On AM437x one of two PRU 106 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
107 items: 107 items:
108 - description: Address and size of t 108 - description: Address and size of the Data RAM0.
109 - description: Address and size of t 109 - description: Address and size of the Data RAM1.
110 - description: | 110 - description: |
111 Address and size of the Shared D 111 Address and size of the Shared Data RAM. Note that on AM437x one
112 of two PRUSS units don't contain 112 of two PRUSS units don't contain Shared RAM, while the second one
113 has it. 113 has it.
114 114
115 reg-names: 115 reg-names:
116 minItems: 2 116 minItems: 2
117 items: 117 items:
118 - const: dram0 118 - const: dram0
119 - const: dram1 119 - const: dram1
120 - const: shrdram2 120 - const: shrdram2
121 121
122 required: 122 required:
123 - reg 123 - reg
124 - reg-names 124 - reg-names
125 125
126 additionalProperties: false 126 additionalProperties: false
127 127
128 cfg@[a-f0-9]+$: 128 cfg@[a-f0-9]+$:
129 description: | 129 description: |
130 PRU-ICSS configuration space. CFG sub-mo 130 PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
131 131
132 type: object 132 type: object
133 additionalProperties: false 133 additionalProperties: false
134 134
135 properties: 135 properties:
136 compatible: 136 compatible:
137 items: 137 items:
138 - const: ti,pruss-cfg 138 - const: ti,pruss-cfg
139 - const: syscon 139 - const: syscon
140 140
141 "#address-cells": 141 "#address-cells":
142 const: 1 142 const: 1
143 143
144 "#size-cells": 144 "#size-cells":
145 const: 1 145 const: 1
146 146
147 reg: 147 reg:
148 maxItems: 1 148 maxItems: 1
149 149
150 ranges: 150 ranges:
151 maxItems: 1 151 maxItems: 1
152 152
153 clocks: 153 clocks:
154 type: object 154 type: object
155 155
156 properties: 156 properties:
157 "#address-cells": 157 "#address-cells":
158 const: 1 158 const: 1
159 159
160 "#size-cells": 160 "#size-cells":
161 const: 0 161 const: 0
162 162
163 patternProperties: 163 patternProperties:
164 coreclk-mux@[a-f0-9]+$: 164 coreclk-mux@[a-f0-9]+$:
165 description: | 165 description: |
166 This is applicable only for ICSS 166 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
167 core clock can be set to one of 167 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
168 ICSSG_ICLK. This node models th 168 ICSSG_ICLK. This node models this clock mux and should have the
169 name "coreclk-mux". 169 name "coreclk-mux".
170 170
171 type: object 171 type: object
172 172
173 properties: 173 properties:
174 '#clock-cells': 174 '#clock-cells':
175 const: 0 175 const: 0
176 176
177 clocks: 177 clocks:
178 items: 178 items:
179 - description: ICSSG_CORE Cl 179 - description: ICSSG_CORE Clock
180 - description: ICSSG_ICLK Cl 180 - description: ICSSG_ICLK Clock
181 181
182 assigned-clocks: 182 assigned-clocks:
183 maxItems: 1 183 maxItems: 1
184 184
185 assigned-clock-parents: 185 assigned-clock-parents:
186 maxItems: 1 186 maxItems: 1
187 description: | 187 description: |
188 Standard assigned-clocks-par 188 Standard assigned-clocks-parents definition used for selecting
189 mux parent (one of the mux i 189 mux parent (one of the mux input).
190 190
191 reg: 191 reg:
192 maxItems: 1 192 maxItems: 1
193 193
194 required: 194 required:
195 - clocks 195 - clocks
196 196
197 additionalProperties: false 197 additionalProperties: false
198 198
199 iepclk-mux@[a-f0-9]+$: 199 iepclk-mux@[a-f0-9]+$:
200 description: | 200 description: |
201 The IEP module can get its clock 201 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
202 CORE_CLK (OCP_CLK in older SoCs) 202 CORE_CLK (OCP_CLK in older SoCs). This node models this clock
203 mux and should have the name "ie 203 mux and should have the name "iepclk-mux".
204 204
205 type: object 205 type: object
206 206
207 properties: 207 properties:
208 '#clock-cells': 208 '#clock-cells':
209 const: 0 209 const: 0
210 210
211 clocks: 211 clocks:
212 items: 212 items:
213 - description: ICSSG_IEP Clo 213 - description: ICSSG_IEP Clock
214 - description: Core Clock (O 214 - description: Core Clock (OCP Clock in older SoCs)
215 215
216 assigned-clocks: 216 assigned-clocks:
217 maxItems: 1 217 maxItems: 1
218 218
219 assigned-clock-parents: 219 assigned-clock-parents:
220 maxItems: 1 220 maxItems: 1
221 description: | 221 description: |
222 Standard assigned-clocks-par 222 Standard assigned-clocks-parents definition used for selecting
223 mux parent (one of the mux i 223 mux parent (one of the mux input).
224 224
225 reg: 225 reg:
226 maxItems: 1 226 maxItems: 1
227 227
228 required: 228 required:
229 - clocks 229 - clocks
230 230
231 additionalProperties: false 231 additionalProperties: false
232 232
233 additionalProperties: false 233 additionalProperties: false
234 234
235 iep@[a-f0-9]+$: 235 iep@[a-f0-9]+$:
236 description: | 236 description: |
237 Industrial Ethernet Peripheral to manage 237 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
238 functions such as time stamping. Each PR 238 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
239 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs 239 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x, J721E & AM64x SoCs).
240 IEP is used for creating PTP clocks and 240 IEP is used for creating PTP clocks and generating PPS signals.
241 241
242 type: object 242 type: object
243 243
244 mii-rt@[a-f0-9]+$: 244 mii-rt@[a-f0-9]+$:
245 description: | 245 description: |
246 Real-Time Ethernet to support multiple i 246 Real-Time Ethernet to support multiple industrial communication protocols.
247 MII-RT sub-module represented as a SysCo 247 MII-RT sub-module represented as a SysCon.
248 248
249 type: object 249 type: object
250 250
251 properties: 251 properties:
252 compatible: 252 compatible:
253 items: 253 items:
254 - const: ti,pruss-mii 254 - const: ti,pruss-mii
255 - const: syscon 255 - const: syscon
256 256
257 reg: 257 reg:
258 maxItems: 1 258 maxItems: 1
259 259
260 additionalProperties: false 260 additionalProperties: false
261 261
262 mii-g-rt@[a-f0-9]+$: 262 mii-g-rt@[a-f0-9]+$:
263 description: | 263 description: |
264 The Real-time Media Independent Interfac 264 The Real-time Media Independent Interface to support multiple industrial
265 communication protocols (G stands for Gi 265 communication protocols (G stands for Gigabit). MII-G-RT sub-module
266 represented as a SysCon. 266 represented as a SysCon.
267 267
268 type: object 268 type: object
269 269
270 properties: 270 properties:
271 compatible: 271 compatible:
272 items: 272 items:
273 - const: ti,pruss-mii-g 273 - const: ti,pruss-mii-g
274 - const: syscon 274 - const: syscon
275 275
276 reg: 276 reg:
277 maxItems: 1 277 maxItems: 1
278 278
279 additionalProperties: false 279 additionalProperties: false
280 280
281 ^pa-stats@[a-f0-9]+$: 281 ^pa-stats@[a-f0-9]+$:
282 description: | 282 description: |
283 PA-STATS sub-module represented as a Sys 283 PA-STATS sub-module represented as a SysCon. PA_STATS is a set of
284 registers where different statistics rel 284 registers where different statistics related to ICSSG, are dumped by
285 ICSSG firmware. This syscon sub-module w 285 ICSSG firmware. This syscon sub-module will help the device to
286 access/read/write those statistics. 286 access/read/write those statistics.
287 287
288 type: object 288 type: object
289 289
290 additionalProperties: false 290 additionalProperties: false
291 291
292 properties: 292 properties:
293 compatible: 293 compatible:
294 items: 294 items:
295 - const: ti,pruss-pa-st 295 - const: ti,pruss-pa-st
296 - const: syscon 296 - const: syscon
297 297
298 reg: 298 reg:
299 maxItems: 1 299 maxItems: 1
300 300
301 interrupt-controller@[a-f0-9]+$: 301 interrupt-controller@[a-f0-9]+$:
302 description: | 302 description: |
303 PRUSS INTC Node. Each PRUSS has a single 303 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
304 that is common to all the PRU cores. Thi 304 that is common to all the PRU cores. This should be represented as an
305 interrupt-controller node. 305 interrupt-controller node.
306 $ref: /schemas/interrupt-controller/ti,pru 306 $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml#
307 type: object 307 type: object
308 308
309 mdio@[a-f0-9]+$: 309 mdio@[a-f0-9]+$:
310 description: | 310 description: |
311 MDIO Node. Each PRUSS has an MDIO module 311 MDIO Node. Each PRUSS has an MDIO module that can be used to control
312 external PHYs. The MDIO module used with 312 external PHYs. The MDIO module used within the PRU-ICSS is an instance of
313 the MDIO Controller used in TI Davinci S 313 the MDIO Controller used in TI Davinci SoCs.
314 $ref: /schemas/net/ti,davinci-mdio.yaml# 314 $ref: /schemas/net/ti,davinci-mdio.yaml#
315 type: object 315 type: object
316 316
317 "^(pru|rtu|txpru)@[0-9a-f]+$": 317 "^(pru|rtu|txpru)@[0-9a-f]+$":
318 description: | 318 description: |
319 PRU Node. Each PRUSS has dual PRU cores, 319 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
320 device through a PRU child node each. Ea 320 device through a PRU child node each. Each node can optionally be rendered
321 inactive by using the standard DT string 321 inactive by using the standard DT string property, "status". The ICSSG IP
322 present on K3 SoCs have additional auxil 322 present on K3 SoCs have additional auxiliary PRU cores with slightly
323 different IP integration. 323 different IP integration.
324 $ref: /schemas/remoteproc/ti,pru-rproc.yam 324 $ref: /schemas/remoteproc/ti,pru-rproc.yaml#
325 type: object 325 type: object
326 326
327 required: 327 required:
328 - compatible 328 - compatible
329 - reg 329 - reg
330 - ranges 330 - ranges
331 331
332 additionalProperties: false 332 additionalProperties: false
333 333
334 # Due to inability of correctly verifying sub- 334 # Due to inability of correctly verifying sub-nodes with an @address through
335 # the "required" list, the required sub-nodes 335 # the "required" list, the required sub-nodes below are commented out for now.
336 336
337 # required: 337 # required:
338 # - memories 338 # - memories
339 # - interrupt-controller 339 # - interrupt-controller
340 # - pru 340 # - pru
341 341
342 allOf: 342 allOf:
343 - if: 343 - if:
344 properties: 344 properties:
345 compatible: 345 compatible:
346 contains: 346 contains:
347 enum: 347 enum:
348 - ti,k2g-pruss 348 - ti,k2g-pruss
349 - ti,am654-icssg 349 - ti,am654-icssg
350 - ti,j721e-icssg 350 - ti,j721e-icssg
351 - ti,am642-icssg 351 - ti,am642-icssg
352 then: 352 then:
353 required: 353 required:
354 - power-domains 354 - power-domains
355 355
356 - if: 356 - if:
357 properties: 357 properties:
358 compatible: 358 compatible:
359 contains: 359 contains:
360 enum: 360 enum:
361 - ti,k2g-pruss 361 - ti,k2g-pruss
362 then: 362 then:
363 required: 363 required:
364 - dma-coherent 364 - dma-coherent
365 365
366 examples: 366 examples:
367 - | 367 - |
368 368
369 /* Example 1 AM33xx PRU-ICSS */ 369 /* Example 1 AM33xx PRU-ICSS */
370 pruss: pruss@0 { 370 pruss: pruss@0 {
371 compatible = "ti,am3356-pruss"; 371 compatible = "ti,am3356-pruss";
372 reg = <0x0 0x80000>; 372 reg = <0x0 0x80000>;
373 #address-cells = <1>; 373 #address-cells = <1>;
374 #size-cells = <1>; 374 #size-cells = <1>;
375 ranges; 375 ranges;
376 376
377 pruss_mem: memories@0 { 377 pruss_mem: memories@0 {
378 reg = <0x0 0x2000>, 378 reg = <0x0 0x2000>,
379 <0x2000 0x2000>, 379 <0x2000 0x2000>,
380 <0x10000 0x3000>; 380 <0x10000 0x3000>;
381 reg-names = "dram0", "dram1", "shr 381 reg-names = "dram0", "dram1", "shrdram2";
382 }; 382 };
383 383
384 pruss_cfg: cfg@26000 { 384 pruss_cfg: cfg@26000 {
385 compatible = "ti,pruss-cfg", "sysc 385 compatible = "ti,pruss-cfg", "syscon";
386 #address-cells = <1>; 386 #address-cells = <1>;
387 #size-cells = <1>; 387 #size-cells = <1>;
388 reg = <0x26000 0x2000>; 388 reg = <0x26000 0x2000>;
389 ranges = <0x00 0x26000 0x2000>; 389 ranges = <0x00 0x26000 0x2000>;
390 390
391 clocks { 391 clocks {
392 #address-cells = <1>; 392 #address-cells = <1>;
393 #size-cells = <0>; 393 #size-cells = <0>;
394 394
395 pruss_iepclk_mux: iepclk-mux@3 395 pruss_iepclk_mux: iepclk-mux@30 {
396 reg = <0x30>; 396 reg = <0x30>;
397 #clock-cells = <0>; 397 #clock-cells = <0>;
398 clocks = <&l3_gclk>, 398 clocks = <&l3_gclk>, /* icss_iep */
399 <&pruss_ocp_gclk> 399 <&pruss_ocp_gclk>; /* icss_ocp */
400 }; 400 };
401 }; 401 };
402 }; 402 };
403 403
404 pruss_mii_rt: mii-rt@32000 { 404 pruss_mii_rt: mii-rt@32000 {
405 compatible = "ti,pruss-mii", "sysc 405 compatible = "ti,pruss-mii", "syscon";
406 reg = <0x32000 0x58>; 406 reg = <0x32000 0x58>;
407 }; 407 };
408 408
409 pruss_intc: interrupt-controller@20000 409 pruss_intc: interrupt-controller@20000 {
410 compatible = "ti,pruss-intc"; 410 compatible = "ti,pruss-intc";
411 reg = <0x20000 0x2000>; 411 reg = <0x20000 0x2000>;
412 interrupt-controller; 412 interrupt-controller;
413 #interrupt-cells = <3>; 413 #interrupt-cells = <3>;
414 interrupts = <20 21 22 23 24 25 26 414 interrupts = <20 21 22 23 24 25 26 27>;
415 interrupt-names = "host_intr0", "h 415 interrupt-names = "host_intr0", "host_intr1",
416 "host_intr2", "h 416 "host_intr2", "host_intr3",
417 "host_intr4", "h 417 "host_intr4", "host_intr5",
418 "host_intr6", "h 418 "host_intr6", "host_intr7";
419 }; 419 };
420 420
421 pru0: pru@34000 { 421 pru0: pru@34000 {
422 compatible = "ti,am3356-pru"; 422 compatible = "ti,am3356-pru";
423 reg = <0x34000 0x2000>, 423 reg = <0x34000 0x2000>,
424 <0x22000 0x400>, 424 <0x22000 0x400>,
425 <0x22400 0x100>; 425 <0x22400 0x100>;
426 reg-names = "iram", "control", "de 426 reg-names = "iram", "control", "debug";
427 firmware-name = "am335x-pru0-fw"; 427 firmware-name = "am335x-pru0-fw";
428 }; 428 };
429 429
430 pru1: pru@38000 { 430 pru1: pru@38000 {
431 compatible = "ti,am3356-pru"; 431 compatible = "ti,am3356-pru";
432 reg = <0x38000 0x2000>, 432 reg = <0x38000 0x2000>,
433 <0x24000 0x400>, 433 <0x24000 0x400>,
434 <0x24400 0x100>; 434 <0x24400 0x100>;
435 reg-names = "iram", "control", "de 435 reg-names = "iram", "control", "debug";
436 firmware-name = "am335x-pru1-fw"; 436 firmware-name = "am335x-pru1-fw";
437 }; 437 };
438 438
439 pruss_mdio: mdio@32400 { 439 pruss_mdio: mdio@32400 {
440 compatible = "ti,davinci_mdio"; 440 compatible = "ti,davinci_mdio";
441 reg = <0x32400 0x90>; 441 reg = <0x32400 0x90>;
442 clocks = <&dpll_core_m4_ck>; 442 clocks = <&dpll_core_m4_ck>;
443 clock-names = "fck"; 443 clock-names = "fck";
444 bus_freq = <1000000>; 444 bus_freq = <1000000>;
445 #address-cells = <1>; 445 #address-cells = <1>;
446 #size-cells = <0>; 446 #size-cells = <0>;
447 }; 447 };
448 }; 448 };
449 449
450 - | 450 - |
451 451
452 /* Example 2 AM43xx PRU-ICSS with PRUSS1 n 452 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */
453 #include <dt-bindings/interrupt-controller 453 #include <dt-bindings/interrupt-controller/arm-gic.h>
454 pruss1: pruss@0 { 454 pruss1: pruss@0 {
455 compatible = "ti,am4376-pruss1"; 455 compatible = "ti,am4376-pruss1";
456 reg = <0x0 0x40000>; 456 reg = <0x0 0x40000>;
457 #address-cells = <1>; 457 #address-cells = <1>;
458 #size-cells = <1>; 458 #size-cells = <1>;
459 ranges; 459 ranges;
460 460
461 pruss1_mem: memories@0 { 461 pruss1_mem: memories@0 {
462 reg = <0x0 0x2000>, 462 reg = <0x0 0x2000>,
463 <0x2000 0x2000>, 463 <0x2000 0x2000>,
464 <0x10000 0x8000>; 464 <0x10000 0x8000>;
465 reg-names = "dram0", "dram1", "shr 465 reg-names = "dram0", "dram1", "shrdram2";
466 }; 466 };
467 467
468 pruss1_cfg: cfg@26000 { 468 pruss1_cfg: cfg@26000 {
469 compatible = "ti,pruss-cfg", "sysc 469 compatible = "ti,pruss-cfg", "syscon";
470 #address-cells = <1>; 470 #address-cells = <1>;
471 #size-cells = <1>; 471 #size-cells = <1>;
472 reg = <0x26000 0x2000>; 472 reg = <0x26000 0x2000>;
473 ranges = <0x00 0x26000 0x2000>; 473 ranges = <0x00 0x26000 0x2000>;
474 474
475 clocks { 475 clocks {
476 #address-cells = <1>; 476 #address-cells = <1>;
477 #size-cells = <0>; 477 #size-cells = <0>;
478 478
479 pruss1_iepclk_mux: iepclk-mux@ 479 pruss1_iepclk_mux: iepclk-mux@30 {
480 reg = <0x30>; 480 reg = <0x30>;
481 #clock-cells = <0>; 481 #clock-cells = <0>;
482 clocks = <&sysclk_div>, 482 clocks = <&sysclk_div>, /* icss_iep */
483 <&pruss_ocp_gclk> 483 <&pruss_ocp_gclk>; /* icss_ocp */
484 }; 484 };
485 }; 485 };
486 }; 486 };
487 487
488 pruss1_mii_rt: mii-rt@32000 { 488 pruss1_mii_rt: mii-rt@32000 {
489 compatible = "ti,pruss-mii", "sysc 489 compatible = "ti,pruss-mii", "syscon";
490 reg = <0x32000 0x58>; 490 reg = <0x32000 0x58>;
491 }; 491 };
492 492
493 pruss1_intc: interrupt-controller@2000 493 pruss1_intc: interrupt-controller@20000 {
494 compatible = "ti,pruss-intc"; 494 compatible = "ti,pruss-intc";
495 reg = <0x20000 0x2000>; 495 reg = <0x20000 0x2000>;
496 interrupt-controller; 496 interrupt-controller;
497 #interrupt-cells = <3>; 497 #interrupt-cells = <3>;
498 interrupts = <GIC_SPI 20 IRQ_TYPE_ 498 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 21 IRQ_TYPE_ 499 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 22 IRQ_TYPE_ 500 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 23 IRQ_TYPE_ 501 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 24 IRQ_TYPE_ 502 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 26 IRQ_TYPE_ 503 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 27 IRQ_TYPE_ 504 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-names = "host_intr0", "h 505 interrupt-names = "host_intr0", "host_intr1",
506 "host_intr2", "h 506 "host_intr2", "host_intr3",
507 "host_intr4", 507 "host_intr4",
508 "host_intr6", "h 508 "host_intr6", "host_intr7";
509 ti,irqs-reserved = /bits/ 8 <0x20> 509 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
510 }; 510 };
511 511
512 pru1_0: pru@34000 { 512 pru1_0: pru@34000 {
513 compatible = "ti,am4376-pru"; 513 compatible = "ti,am4376-pru";
514 reg = <0x34000 0x3000>, 514 reg = <0x34000 0x3000>,
515 <0x22000 0x400>, 515 <0x22000 0x400>,
516 <0x22400 0x100>; 516 <0x22400 0x100>;
517 reg-names = "iram", "control", "de 517 reg-names = "iram", "control", "debug";
518 firmware-name = "am437x-pru1_0-fw" 518 firmware-name = "am437x-pru1_0-fw";
519 }; 519 };
520 520
521 pru1_1: pru@38000 { 521 pru1_1: pru@38000 {
522 compatible = "ti,am4376-pru"; 522 compatible = "ti,am4376-pru";
523 reg = <0x38000 0x3000>, 523 reg = <0x38000 0x3000>,
524 <0x24000 0x400>, 524 <0x24000 0x400>,
525 <0x24400 0x100>; 525 <0x24400 0x100>;
526 reg-names = "iram", "control", "de 526 reg-names = "iram", "control", "debug";
527 firmware-name = "am437x-pru1_1-fw" 527 firmware-name = "am437x-pru1_1-fw";
528 }; 528 };
529 529
530 pruss1_mdio: mdio@32400 { 530 pruss1_mdio: mdio@32400 {
531 compatible = "ti,davinci_mdio"; 531 compatible = "ti,davinci_mdio";
532 reg = <0x32400 0x90>; 532 reg = <0x32400 0x90>;
533 clocks = <&dpll_core_m4_ck>; 533 clocks = <&dpll_core_m4_ck>;
534 clock-names = "fck"; 534 clock-names = "fck";
535 bus_freq = <1000000>; 535 bus_freq = <1000000>;
536 #address-cells = <1>; 536 #address-cells = <1>;
537 #size-cells = <0>; 537 #size-cells = <0>;
538 }; 538 };
539 }; 539 };
540 540
541 ... 541 ...
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