1 LogicoreIP designed compatible with Xilinx ZYN 1 LogicoreIP designed compatible with Xilinx ZYNQ family.
2 ---------------------------------------------- 2 -------------------------------------------------------
3 3
4 General concept 4 General concept
5 --------------- 5 ---------------
6 6
7 LogicoreIP design to provide the isolation bet 7 LogicoreIP design to provide the isolation between processing system
8 and programmable logic. Also provides the list 8 and programmable logic. Also provides the list of register set to configure
9 the frequency. 9 the frequency.
10 10
11 Required properties: 11 Required properties:
12 - compatible: shall be one of: 12 - compatible: shall be one of:
13 "xlnx,vcu" 13 "xlnx,vcu"
14 "xlnx,vcu-logicoreip-1.0" 14 "xlnx,vcu-logicoreip-1.0"
15 - reg : The base offset and size of the VCU_PL 15 - reg : The base offset and size of the VCU_PL_SLCR register space.
16 - clocks: phandle for aclk and pll_ref clockso 16 - clocks: phandle for aclk and pll_ref clocksource
17 - clock-names: The identification string, "acl 17 - clock-names: The identification string, "aclk", is always required for
18 the axi clock. "pll_ref" is required for pl 18 the axi clock. "pll_ref" is required for pll.
19 Example: 19 Example:
20 20
21 xlnx_vcu: vcu@a0040000 { 21 xlnx_vcu: vcu@a0040000 {
22 compatible = "xlnx,vcu-logicor 22 compatible = "xlnx,vcu-logicoreip-1.0";
23 reg = <0x0 0xa0040000 0x0 0x10 23 reg = <0x0 0xa0040000 0x0 0x1000>;
24 clocks = <&si570_1>, <&clkc 71 24 clocks = <&si570_1>, <&clkc 71>;
25 clock-names = "pll_ref", "aclk 25 clock-names = "pll_ref", "aclk";
26 }; 26 };
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