1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,s 4 $id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale Synchronous Audio Interface ( 7 title: Freescale Synchronous Audio Interface (SAI).
8 8
9 maintainers: 9 maintainers:
10 - Shengjiu Wang <shengjiu.wang@nxp.com> 10 - Shengjiu Wang <shengjiu.wang@nxp.com>
11 11
12 description: | 12 description: |
13 The SAI is based on I2S module that used com 13 The SAI is based on I2S module that used communicating with audio codecs,
14 which provides a synchronous audio interface 14 which provides a synchronous audio interface that supports fullduplex
15 serial interfaces with frame synchronization 15 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16 codec/DSP interfaces. 16 codec/DSP interfaces.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 oneOf: 20 oneOf:
21 - items: !! 21 - enum:
22 - enum: !! 22 - fsl,vf610-sai
23 - fsl,imx6ul-sai !! 23 - fsl,imx6sx-sai
24 - fsl,imx7d-sai !! 24 - fsl,imx6ul-sai
25 - const: fsl,imx6sx-sai !! 25 - fsl,imx7ulp-sai
26 !! 26 - fsl,imx8mq-sai
>> 27 - fsl,imx8qm-sai
>> 28 - fsl,imx8ulp-sai
27 - items: 29 - items:
28 - enum: 30 - enum:
29 - fsl,imx8mm-sai 31 - fsl,imx8mm-sai
30 - fsl,imx8mn-sai 32 - fsl,imx8mn-sai
31 - fsl,imx8mp-sai 33 - fsl,imx8mp-sai
32 - const: fsl,imx8mq-sai 34 - const: fsl,imx8mq-sai
33 35
34 - items: <<
35 - enum: <<
36 - fsl,imx6sx-sai <<
37 - fsl,imx7ulp-sai <<
38 - fsl,imx8mq-sai <<
39 - fsl,imx8qm-sai <<
40 - fsl,imx8ulp-sai <<
41 - fsl,imx93-sai <<
42 - fsl,imx95-sai <<
43 - fsl,vf610-sai <<
44 <<
45 reg: 36 reg:
46 maxItems: 1 37 maxItems: 1
47 38
>> 39 interrupts:
>> 40 items:
>> 41 - description: receive and transmit interrupt
>> 42
>> 43 dmas:
>> 44 maxItems: 2
>> 45
>> 46 dma-names:
>> 47 maxItems: 2
>> 48
48 clocks: 49 clocks:
49 items: 50 items:
50 - description: The ipg clock for registe 51 - description: The ipg clock for register access
51 - description: master clock source 0 (ob 52 - description: master clock source 0 (obsoleted)
52 - description: master clock source 1 53 - description: master clock source 1
53 - description: master clock source 2 54 - description: master clock source 2
54 - description: master clock source 3 55 - description: master clock source 3
55 - description: PLL clock source for 8kHz 56 - description: PLL clock source for 8kHz series
56 - description: PLL clock source for 11kH 57 - description: PLL clock source for 11kHz series
57 minItems: 4 58 minItems: 4
58 59
59 clock-names: 60 clock-names:
60 oneOf: 61 oneOf:
61 - items: 62 - items:
62 - const: bus 63 - const: bus
63 - const: mclk0 64 - const: mclk0
64 - const: mclk1 65 - const: mclk1
65 - const: mclk2 66 - const: mclk2
66 - const: mclk3 67 - const: mclk3
67 - const: pll8k 68 - const: pll8k
68 - const: pll11k 69 - const: pll11k
69 minItems: 5 !! 70 minItems: 4
70 - items: 71 - items:
71 - const: bus 72 - const: bus
72 - const: mclk1 73 - const: mclk1
73 - const: mclk2 74 - const: mclk2
74 - const: mclk3 75 - const: mclk3
75 - const: pll8k 76 - const: pll8k
76 - const: pll11k 77 - const: pll11k
77 minItems: 4 78 minItems: 4
78 79
79 power-domains: !! 80 lsb-first:
80 maxItems: 1 <<
81 <<
82 dmas: <<
83 minItems: 1 <<
84 maxItems: 2 <<
85 <<
86 dma-names: <<
87 minItems: 1 <<
88 items: <<
89 - enum: [ rx, tx ] <<
90 - const: tx <<
91 <<
92 interrupts: <<
93 items: <<
94 - description: receive and transmit inte <<
95 <<
96 big-endian: <<
97 description: | 81 description: |
98 required if all the SAI registers are bi !! 82 Configures whether the LSB or the MSB is transmitted
>> 83 first for the fifo data. If this property is absent,
>> 84 the MSB is transmitted first as default, or the LSB
>> 85 is transmitted first.
99 type: boolean 86 type: boolean
100 87
101 fsl,dataline: !! 88 big-endian:
102 $ref: /schemas/types.yaml#/definitions/uin <<
103 description: | 89 description: |
104 Configure the dataline. It has 3 value f !! 90 required if all the SAI registers are big-endian rather than little-endian.
105 maxItems: 16 <<
106 items: <<
107 items: <<
108 - description: format Default(0), I2S( <<
109 enum: [0, 1, 2] <<
110 - description: dataline mask for 'rx' <<
111 - description: dataline mask for 'tx' <<
112 <<
113 fsl,sai-mclk-direction-output: <<
114 description: SAI will output the SAI MCLK <<
115 type: boolean 91 type: boolean
116 92
117 fsl,sai-synchronous-rx: 93 fsl,sai-synchronous-rx:
118 description: | 94 description: |
119 SAI will work in the synchronous mode (s 95 SAI will work in the synchronous mode (sync Tx with Rx) which means
120 both the transmitter and the receiver wi 96 both the transmitter and the receiver will send and receive data by
121 following receiver's bit clocks and fram 97 following receiver's bit clocks and frame sync clocks.
122 type: boolean 98 type: boolean
123 99
124 fsl,sai-asynchronous: 100 fsl,sai-asynchronous:
125 description: | 101 description: |
126 SAI will work in the asynchronous mode, 102 SAI will work in the asynchronous mode, which means both transmitter
127 and receiver will send and receive data 103 and receiver will send and receive data by following their own bit clocks
128 and frame sync clocks separately. 104 and frame sync clocks separately.
129 If both fsl,sai-asynchronous and fsl,sai 105 If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
130 default synchronous mode (sync Rx with T 106 default synchronous mode (sync Rx with Tx) will be used, which means both
131 transmitter and receiver will send and r 107 transmitter and receiver will send and receive data by following clocks
132 of transmitter. 108 of transmitter.
133 type: boolean 109 type: boolean
134 110
135 fsl,shared-interrupt: !! 111 fsl,dataline:
136 description: Interrupt is shared with othe !! 112 $ref: /schemas/types.yaml#/definitions/uint32-matrix
>> 113 description: |
>> 114 Configure the dataline. It has 3 value for each configuration
>> 115 maxItems: 16
>> 116 items:
>> 117 items:
>> 118 - description: format Default(0), I2S(1) or PDM(2)
>> 119 enum: [0, 1, 2]
>> 120 - description: dataline mask for 'rx'
>> 121 - description: dataline mask for 'tx'
>> 122
>> 123 fsl,sai-mclk-direction-output:
>> 124 description: SAI will output the SAI MCLK clock.
137 type: boolean 125 type: boolean
138 126
139 lsb-first: !! 127 fsl,shared-interrupt:
140 description: | !! 128 description: Interrupt is shared with other modules.
141 Configures whether the LSB or the MSB is <<
142 first for the fifo data. If this propert <<
143 the MSB is transmitted first as default, <<
144 is transmitted first. <<
145 type: boolean 129 type: boolean
146 130
147 "#sound-dai-cells": 131 "#sound-dai-cells":
148 const: 0 132 const: 0
149 description: optional, some dts node didn' 133 description: optional, some dts node didn't add it.
150 134
151 allOf: 135 allOf:
152 - $ref: dai-common.yaml# !! 136 - if:
>> 137 properties:
>> 138 compatible:
>> 139 contains:
>> 140 const: fsl,vf610-sai
>> 141 then:
>> 142 properties:
>> 143 dmas:
>> 144 items:
>> 145 - description: DMA controller phandle and request line for TX
>> 146 - description: DMA controller phandle and request line for RX
>> 147 dma-names:
>> 148 items:
>> 149 - const: tx
>> 150 - const: rx
>> 151 else:
>> 152 properties:
>> 153 dmas:
>> 154 items:
>> 155 - description: DMA controller phandle and request line for RX
>> 156 - description: DMA controller phandle and request line for TX
>> 157 dma-names:
>> 158 items:
>> 159 - const: rx
>> 160 - const: tx
153 - if: 161 - if:
154 required: 162 required:
155 - fsl,sai-asynchronous 163 - fsl,sai-asynchronous
156 then: 164 then:
157 properties: 165 properties:
158 fsl,sai-synchronous-rx: false 166 fsl,sai-synchronous-rx: false
159 167
160 required: 168 required:
161 - compatible 169 - compatible
162 - reg 170 - reg
163 - clocks !! 171 - interrupts
164 - clock-names <<
165 - dmas 172 - dmas
166 - dma-names 173 - dma-names
167 - interrupts !! 174 - clocks
>> 175 - clock-names
168 176
169 unevaluatedProperties: false !! 177 additionalProperties: false
170 178
171 examples: 179 examples:
172 - | 180 - |
173 #include <dt-bindings/interrupt-controller 181 #include <dt-bindings/interrupt-controller/arm-gic.h>
174 #include <dt-bindings/clock/vf610-clock.h> 182 #include <dt-bindings/clock/vf610-clock.h>
175 sai2: sai@40031000 { 183 sai2: sai@40031000 {
176 compatible = "fsl,vf610-sai"; 184 compatible = "fsl,vf610-sai";
177 reg = <0x40031000 0x1000>; 185 reg = <0x40031000 0x1000>;
178 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; 186 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
179 pinctrl-names = "default"; 187 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_sai2_1>; 188 pinctrl-0 = <&pinctrl_sai2_1>;
181 clocks = <&clks VF610_CLK_PLATFORM_BUS 189 clocks = <&clks VF610_CLK_PLATFORM_BUS>,
182 <&clks VF610_CLK_SAI2>, 190 <&clks VF610_CLK_SAI2>,
183 <&clks 0>, <&clks 0>; 191 <&clks 0>, <&clks 0>;
184 clock-names = "bus", "mclk1", "mclk2", 192 clock-names = "bus", "mclk1", "mclk2", "mclk3";
185 dma-names = "rx", "tx"; !! 193 dma-names = "tx", "rx";
186 dmas = <&edma0 0 20>, <&edma0 0 21>; !! 194 dmas = <&edma0 0 21>,
>> 195 <&edma0 0 20>;
187 big-endian; 196 big-endian;
188 lsb-first; 197 lsb-first;
189 }; 198 };
190 199
191 - | 200 - |
192 #include <dt-bindings/interrupt-controller 201 #include <dt-bindings/interrupt-controller/arm-gic.h>
193 #include <dt-bindings/clock/imx8mm-clock.h 202 #include <dt-bindings/clock/imx8mm-clock.h>
194 sai1: sai@30010000 { 203 sai1: sai@30010000 {
195 compatible = "fsl,imx8mm-sai", "fsl,im 204 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
196 reg = <0x30010000 0x10000>; 205 reg = <0x30010000 0x10000>;
197 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVE 206 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 207 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
199 <&clk IMX8MM_CLK_DUMMY>, 208 <&clk IMX8MM_CLK_DUMMY>,
200 <&clk IMX8MM_CLK_SAI1_ROOT>, 209 <&clk IMX8MM_CLK_SAI1_ROOT>,
201 <&clk IMX8MM_CLK_DUMMY>, <&cl 210 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
202 clock-names = "bus", "mclk0", "mclk1", 211 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
203 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 212 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
204 dma-names = "rx", "tx"; 213 dma-names = "rx", "tx";
205 fsl,dataline = <1 0xff 0xff 2 0xff 0x1 214 fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
206 #sound-dai-cells = <0>; 215 #sound-dai-cells = <0>;
207 }; 216 };
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