1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,s 4 $id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale Synchronous Audio Interface ( 7 title: Freescale Synchronous Audio Interface (SAI).
8 8
9 maintainers: 9 maintainers:
10 - Shengjiu Wang <shengjiu.wang@nxp.com> 10 - Shengjiu Wang <shengjiu.wang@nxp.com>
11 11
12 description: | 12 description: |
13 The SAI is based on I2S module that used com 13 The SAI is based on I2S module that used communicating with audio codecs,
14 which provides a synchronous audio interface 14 which provides a synchronous audio interface that supports fullduplex
15 serial interfaces with frame synchronization 15 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16 codec/DSP interfaces. 16 codec/DSP interfaces.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 oneOf: 20 oneOf:
21 - items: 21 - items:
22 - enum: 22 - enum:
23 - fsl,imx6ul-sai 23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai 24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai 25 - const: fsl,imx6sx-sai
26 26
27 - items: 27 - items:
28 - enum: 28 - enum:
29 - fsl,imx8mm-sai 29 - fsl,imx8mm-sai
30 - fsl,imx8mn-sai 30 - fsl,imx8mn-sai
31 - fsl,imx8mp-sai 31 - fsl,imx8mp-sai
32 - const: fsl,imx8mq-sai 32 - const: fsl,imx8mq-sai
33 33
34 - items: 34 - items:
35 - enum: 35 - enum:
36 - fsl,imx6sx-sai 36 - fsl,imx6sx-sai
37 - fsl,imx7ulp-sai 37 - fsl,imx7ulp-sai
38 - fsl,imx8mq-sai 38 - fsl,imx8mq-sai
39 - fsl,imx8qm-sai 39 - fsl,imx8qm-sai
40 - fsl,imx8ulp-sai 40 - fsl,imx8ulp-sai
41 - fsl,imx93-sai 41 - fsl,imx93-sai
42 - fsl,imx95-sai <<
43 - fsl,vf610-sai 42 - fsl,vf610-sai
44 43
45 reg: 44 reg:
46 maxItems: 1 45 maxItems: 1
47 46
48 clocks: 47 clocks:
49 items: 48 items:
50 - description: The ipg clock for registe 49 - description: The ipg clock for register access
51 - description: master clock source 0 (ob 50 - description: master clock source 0 (obsoleted)
52 - description: master clock source 1 51 - description: master clock source 1
53 - description: master clock source 2 52 - description: master clock source 2
54 - description: master clock source 3 53 - description: master clock source 3
55 - description: PLL clock source for 8kHz 54 - description: PLL clock source for 8kHz series
56 - description: PLL clock source for 11kH 55 - description: PLL clock source for 11kHz series
57 minItems: 4 56 minItems: 4
58 57
59 clock-names: 58 clock-names:
60 oneOf: 59 oneOf:
61 - items: 60 - items:
62 - const: bus 61 - const: bus
63 - const: mclk0 62 - const: mclk0
64 - const: mclk1 63 - const: mclk1
65 - const: mclk2 64 - const: mclk2
66 - const: mclk3 65 - const: mclk3
67 - const: pll8k 66 - const: pll8k
68 - const: pll11k 67 - const: pll11k
69 minItems: 5 68 minItems: 5
70 - items: 69 - items:
71 - const: bus 70 - const: bus
72 - const: mclk1 71 - const: mclk1
73 - const: mclk2 72 - const: mclk2
74 - const: mclk3 73 - const: mclk3
75 - const: pll8k 74 - const: pll8k
76 - const: pll11k 75 - const: pll11k
77 minItems: 4 76 minItems: 4
78 77
79 power-domains: <<
80 maxItems: 1 <<
81 <<
82 dmas: 78 dmas:
83 minItems: 1 <<
84 maxItems: 2 79 maxItems: 2
85 80
86 dma-names: 81 dma-names:
87 minItems: 1 !! 82 maxItems: 2
88 items: <<
89 - enum: [ rx, tx ] <<
90 - const: tx <<
91 83
92 interrupts: 84 interrupts:
93 items: 85 items:
94 - description: receive and transmit inte 86 - description: receive and transmit interrupt
95 87
96 big-endian: 88 big-endian:
97 description: | 89 description: |
98 required if all the SAI registers are bi 90 required if all the SAI registers are big-endian rather than little-endian.
99 type: boolean 91 type: boolean
100 92
101 fsl,dataline: 93 fsl,dataline:
102 $ref: /schemas/types.yaml#/definitions/uin 94 $ref: /schemas/types.yaml#/definitions/uint32-matrix
103 description: | 95 description: |
104 Configure the dataline. It has 3 value f 96 Configure the dataline. It has 3 value for each configuration
105 maxItems: 16 97 maxItems: 16
106 items: 98 items:
107 items: 99 items:
108 - description: format Default(0), I2S( 100 - description: format Default(0), I2S(1) or PDM(2)
109 enum: [0, 1, 2] 101 enum: [0, 1, 2]
110 - description: dataline mask for 'rx' 102 - description: dataline mask for 'rx'
111 - description: dataline mask for 'tx' 103 - description: dataline mask for 'tx'
112 104
113 fsl,sai-mclk-direction-output: 105 fsl,sai-mclk-direction-output:
114 description: SAI will output the SAI MCLK 106 description: SAI will output the SAI MCLK clock.
115 type: boolean 107 type: boolean
116 108
117 fsl,sai-synchronous-rx: 109 fsl,sai-synchronous-rx:
118 description: | 110 description: |
119 SAI will work in the synchronous mode (s 111 SAI will work in the synchronous mode (sync Tx with Rx) which means
120 both the transmitter and the receiver wi 112 both the transmitter and the receiver will send and receive data by
121 following receiver's bit clocks and fram 113 following receiver's bit clocks and frame sync clocks.
122 type: boolean 114 type: boolean
123 115
124 fsl,sai-asynchronous: 116 fsl,sai-asynchronous:
125 description: | 117 description: |
126 SAI will work in the asynchronous mode, 118 SAI will work in the asynchronous mode, which means both transmitter
127 and receiver will send and receive data 119 and receiver will send and receive data by following their own bit clocks
128 and frame sync clocks separately. 120 and frame sync clocks separately.
129 If both fsl,sai-asynchronous and fsl,sai 121 If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
130 default synchronous mode (sync Rx with T 122 default synchronous mode (sync Rx with Tx) will be used, which means both
131 transmitter and receiver will send and r 123 transmitter and receiver will send and receive data by following clocks
132 of transmitter. 124 of transmitter.
133 type: boolean 125 type: boolean
134 126
135 fsl,shared-interrupt: 127 fsl,shared-interrupt:
136 description: Interrupt is shared with othe 128 description: Interrupt is shared with other modules.
137 type: boolean 129 type: boolean
138 130
139 lsb-first: 131 lsb-first:
140 description: | 132 description: |
141 Configures whether the LSB or the MSB is 133 Configures whether the LSB or the MSB is transmitted
142 first for the fifo data. If this propert 134 first for the fifo data. If this property is absent,
143 the MSB is transmitted first as default, 135 the MSB is transmitted first as default, or the LSB
144 is transmitted first. 136 is transmitted first.
145 type: boolean 137 type: boolean
146 138
147 "#sound-dai-cells": 139 "#sound-dai-cells":
148 const: 0 140 const: 0
149 description: optional, some dts node didn' 141 description: optional, some dts node didn't add it.
150 142
151 allOf: 143 allOf:
152 - $ref: dai-common.yaml# 144 - $ref: dai-common.yaml#
153 - if: 145 - if:
>> 146 properties:
>> 147 compatible:
>> 148 contains:
>> 149 const: fsl,vf610-sai
>> 150 then:
>> 151 properties:
>> 152 dmas:
>> 153 items:
>> 154 - description: DMA controller phandle and request line for TX
>> 155 - description: DMA controller phandle and request line for RX
>> 156 dma-names:
>> 157 items:
>> 158 - const: tx
>> 159 - const: rx
>> 160 else:
>> 161 properties:
>> 162 dmas:
>> 163 items:
>> 164 - description: DMA controller phandle and request line for RX
>> 165 - description: DMA controller phandle and request line for TX
>> 166 dma-names:
>> 167 items:
>> 168 - const: rx
>> 169 - const: tx
>> 170 - if:
154 required: 171 required:
155 - fsl,sai-asynchronous 172 - fsl,sai-asynchronous
156 then: 173 then:
157 properties: 174 properties:
158 fsl,sai-synchronous-rx: false 175 fsl,sai-synchronous-rx: false
159 176
160 required: 177 required:
161 - compatible 178 - compatible
162 - reg 179 - reg
163 - clocks 180 - clocks
164 - clock-names 181 - clock-names
165 - dmas 182 - dmas
166 - dma-names 183 - dma-names
167 - interrupts 184 - interrupts
168 185
169 unevaluatedProperties: false 186 unevaluatedProperties: false
170 187
171 examples: 188 examples:
172 - | 189 - |
173 #include <dt-bindings/interrupt-controller 190 #include <dt-bindings/interrupt-controller/arm-gic.h>
174 #include <dt-bindings/clock/vf610-clock.h> 191 #include <dt-bindings/clock/vf610-clock.h>
175 sai2: sai@40031000 { 192 sai2: sai@40031000 {
176 compatible = "fsl,vf610-sai"; 193 compatible = "fsl,vf610-sai";
177 reg = <0x40031000 0x1000>; 194 reg = <0x40031000 0x1000>;
178 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; 195 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
179 pinctrl-names = "default"; 196 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_sai2_1>; 197 pinctrl-0 = <&pinctrl_sai2_1>;
181 clocks = <&clks VF610_CLK_PLATFORM_BUS 198 clocks = <&clks VF610_CLK_PLATFORM_BUS>,
182 <&clks VF610_CLK_SAI2>, 199 <&clks VF610_CLK_SAI2>,
183 <&clks 0>, <&clks 0>; 200 <&clks 0>, <&clks 0>;
184 clock-names = "bus", "mclk1", "mclk2", 201 clock-names = "bus", "mclk1", "mclk2", "mclk3";
185 dma-names = "rx", "tx"; !! 202 dma-names = "tx", "rx";
186 dmas = <&edma0 0 20>, <&edma0 0 21>; !! 203 dmas = <&edma0 0 21>,
>> 204 <&edma0 0 20>;
187 big-endian; 205 big-endian;
188 lsb-first; 206 lsb-first;
189 }; 207 };
190 208
191 - | 209 - |
192 #include <dt-bindings/interrupt-controller 210 #include <dt-bindings/interrupt-controller/arm-gic.h>
193 #include <dt-bindings/clock/imx8mm-clock.h 211 #include <dt-bindings/clock/imx8mm-clock.h>
194 sai1: sai@30010000 { 212 sai1: sai@30010000 {
195 compatible = "fsl,imx8mm-sai", "fsl,im 213 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
196 reg = <0x30010000 0x10000>; 214 reg = <0x30010000 0x10000>;
197 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVE 215 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 216 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
199 <&clk IMX8MM_CLK_DUMMY>, 217 <&clk IMX8MM_CLK_DUMMY>,
200 <&clk IMX8MM_CLK_SAI1_ROOT>, 218 <&clk IMX8MM_CLK_SAI1_ROOT>,
201 <&clk IMX8MM_CLK_DUMMY>, <&cl 219 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
202 clock-names = "bus", "mclk0", "mclk1", 220 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
203 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 221 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
204 dma-names = "rx", "tx"; 222 dma-names = "rx", "tx";
205 fsl,dataline = <1 0xff 0xff 2 0xff 0x1 223 fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
206 #sound-dai-cells = <0>; 224 #sound-dai-cells = <0>;
207 }; 225 };
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