1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,s 4 $id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale Synchronous Audio Interface ( 7 title: Freescale Synchronous Audio Interface (SAI).
8 8
9 maintainers: 9 maintainers:
10 - Shengjiu Wang <shengjiu.wang@nxp.com> 10 - Shengjiu Wang <shengjiu.wang@nxp.com>
11 11
12 description: | 12 description: |
13 The SAI is based on I2S module that used com 13 The SAI is based on I2S module that used communicating with audio codecs,
14 which provides a synchronous audio interface 14 which provides a synchronous audio interface that supports fullduplex
15 serial interfaces with frame synchronization 15 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16 codec/DSP interfaces. 16 codec/DSP interfaces.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 oneOf: 20 oneOf:
21 - items: 21 - items:
22 - enum: 22 - enum:
23 - fsl,imx6ul-sai 23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai 24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai 25 - const: fsl,imx6sx-sai
26 26
27 - items: 27 - items:
28 - enum: 28 - enum:
29 - fsl,imx8mm-sai 29 - fsl,imx8mm-sai
30 - fsl,imx8mn-sai 30 - fsl,imx8mn-sai
31 - fsl,imx8mp-sai 31 - fsl,imx8mp-sai
32 - const: fsl,imx8mq-sai 32 - const: fsl,imx8mq-sai
33 33
34 - items: 34 - items:
35 - enum: 35 - enum:
36 - fsl,imx6sx-sai 36 - fsl,imx6sx-sai
37 - fsl,imx7ulp-sai 37 - fsl,imx7ulp-sai
38 - fsl,imx8mq-sai 38 - fsl,imx8mq-sai
39 - fsl,imx8qm-sai 39 - fsl,imx8qm-sai
40 - fsl,imx8ulp-sai 40 - fsl,imx8ulp-sai
41 - fsl,imx93-sai 41 - fsl,imx93-sai
42 - fsl,imx95-sai <<
43 - fsl,vf610-sai 42 - fsl,vf610-sai
44 43
45 reg: 44 reg:
46 maxItems: 1 45 maxItems: 1
47 46
48 clocks: 47 clocks:
49 items: 48 items:
50 - description: The ipg clock for registe 49 - description: The ipg clock for register access
51 - description: master clock source 0 (ob 50 - description: master clock source 0 (obsoleted)
52 - description: master clock source 1 51 - description: master clock source 1
53 - description: master clock source 2 52 - description: master clock source 2
54 - description: master clock source 3 53 - description: master clock source 3
55 - description: PLL clock source for 8kHz 54 - description: PLL clock source for 8kHz series
56 - description: PLL clock source for 11kH 55 - description: PLL clock source for 11kHz series
57 minItems: 4 56 minItems: 4
58 57
59 clock-names: 58 clock-names:
60 oneOf: 59 oneOf:
61 - items: 60 - items:
62 - const: bus 61 - const: bus
63 - const: mclk0 62 - const: mclk0
64 - const: mclk1 63 - const: mclk1
65 - const: mclk2 64 - const: mclk2
66 - const: mclk3 65 - const: mclk3
67 - const: pll8k 66 - const: pll8k
68 - const: pll11k 67 - const: pll11k
69 minItems: 5 68 minItems: 5
70 - items: 69 - items:
71 - const: bus 70 - const: bus
72 - const: mclk1 71 - const: mclk1
73 - const: mclk2 72 - const: mclk2
74 - const: mclk3 73 - const: mclk3
75 - const: pll8k 74 - const: pll8k
76 - const: pll11k 75 - const: pll11k
77 minItems: 4 76 minItems: 4
78 77
79 power-domains: <<
80 maxItems: 1 <<
81 <<
82 dmas: 78 dmas:
83 minItems: 1 !! 79 items:
84 maxItems: 2 !! 80 - description: DMA controller phandle and request line for RX
>> 81 - description: DMA controller phandle and request line for TX
85 82
86 dma-names: 83 dma-names:
87 minItems: 1 <<
88 items: 84 items:
89 - enum: [ rx, tx ] !! 85 - const: rx
90 - const: tx 86 - const: tx
91 87
92 interrupts: 88 interrupts:
93 items: 89 items:
94 - description: receive and transmit inte 90 - description: receive and transmit interrupt
95 91
96 big-endian: 92 big-endian:
97 description: | 93 description: |
98 required if all the SAI registers are bi 94 required if all the SAI registers are big-endian rather than little-endian.
99 type: boolean 95 type: boolean
100 96
101 fsl,dataline: 97 fsl,dataline:
102 $ref: /schemas/types.yaml#/definitions/uin 98 $ref: /schemas/types.yaml#/definitions/uint32-matrix
103 description: | 99 description: |
104 Configure the dataline. It has 3 value f 100 Configure the dataline. It has 3 value for each configuration
105 maxItems: 16 101 maxItems: 16
106 items: 102 items:
107 items: 103 items:
108 - description: format Default(0), I2S( 104 - description: format Default(0), I2S(1) or PDM(2)
109 enum: [0, 1, 2] 105 enum: [0, 1, 2]
110 - description: dataline mask for 'rx' 106 - description: dataline mask for 'rx'
111 - description: dataline mask for 'tx' 107 - description: dataline mask for 'tx'
112 108
113 fsl,sai-mclk-direction-output: 109 fsl,sai-mclk-direction-output:
114 description: SAI will output the SAI MCLK 110 description: SAI will output the SAI MCLK clock.
115 type: boolean 111 type: boolean
116 112
117 fsl,sai-synchronous-rx: 113 fsl,sai-synchronous-rx:
118 description: | 114 description: |
119 SAI will work in the synchronous mode (s 115 SAI will work in the synchronous mode (sync Tx with Rx) which means
120 both the transmitter and the receiver wi 116 both the transmitter and the receiver will send and receive data by
121 following receiver's bit clocks and fram 117 following receiver's bit clocks and frame sync clocks.
122 type: boolean 118 type: boolean
123 119
124 fsl,sai-asynchronous: 120 fsl,sai-asynchronous:
125 description: | 121 description: |
126 SAI will work in the asynchronous mode, 122 SAI will work in the asynchronous mode, which means both transmitter
127 and receiver will send and receive data 123 and receiver will send and receive data by following their own bit clocks
128 and frame sync clocks separately. 124 and frame sync clocks separately.
129 If both fsl,sai-asynchronous and fsl,sai 125 If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
130 default synchronous mode (sync Rx with T 126 default synchronous mode (sync Rx with Tx) will be used, which means both
131 transmitter and receiver will send and r 127 transmitter and receiver will send and receive data by following clocks
132 of transmitter. 128 of transmitter.
133 type: boolean 129 type: boolean
134 130
135 fsl,shared-interrupt: 131 fsl,shared-interrupt:
136 description: Interrupt is shared with othe 132 description: Interrupt is shared with other modules.
137 type: boolean 133 type: boolean
138 134
139 lsb-first: 135 lsb-first:
140 description: | 136 description: |
141 Configures whether the LSB or the MSB is 137 Configures whether the LSB or the MSB is transmitted
142 first for the fifo data. If this propert 138 first for the fifo data. If this property is absent,
143 the MSB is transmitted first as default, 139 the MSB is transmitted first as default, or the LSB
144 is transmitted first. 140 is transmitted first.
145 type: boolean 141 type: boolean
146 142
147 "#sound-dai-cells": 143 "#sound-dai-cells":
148 const: 0 144 const: 0
149 description: optional, some dts node didn' 145 description: optional, some dts node didn't add it.
150 146
151 allOf: 147 allOf:
152 - $ref: dai-common.yaml# 148 - $ref: dai-common.yaml#
153 - if: 149 - if:
154 required: 150 required:
155 - fsl,sai-asynchronous 151 - fsl,sai-asynchronous
156 then: 152 then:
157 properties: 153 properties:
158 fsl,sai-synchronous-rx: false 154 fsl,sai-synchronous-rx: false
159 155
160 required: 156 required:
161 - compatible 157 - compatible
162 - reg 158 - reg
163 - clocks 159 - clocks
164 - clock-names 160 - clock-names
165 - dmas 161 - dmas
166 - dma-names 162 - dma-names
167 - interrupts 163 - interrupts
168 164
169 unevaluatedProperties: false 165 unevaluatedProperties: false
170 166
171 examples: 167 examples:
172 - | 168 - |
173 #include <dt-bindings/interrupt-controller 169 #include <dt-bindings/interrupt-controller/arm-gic.h>
174 #include <dt-bindings/clock/vf610-clock.h> 170 #include <dt-bindings/clock/vf610-clock.h>
175 sai2: sai@40031000 { 171 sai2: sai@40031000 {
176 compatible = "fsl,vf610-sai"; 172 compatible = "fsl,vf610-sai";
177 reg = <0x40031000 0x1000>; 173 reg = <0x40031000 0x1000>;
178 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; 174 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
179 pinctrl-names = "default"; 175 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_sai2_1>; 176 pinctrl-0 = <&pinctrl_sai2_1>;
181 clocks = <&clks VF610_CLK_PLATFORM_BUS 177 clocks = <&clks VF610_CLK_PLATFORM_BUS>,
182 <&clks VF610_CLK_SAI2>, 178 <&clks VF610_CLK_SAI2>,
183 <&clks 0>, <&clks 0>; 179 <&clks 0>, <&clks 0>;
184 clock-names = "bus", "mclk1", "mclk2", 180 clock-names = "bus", "mclk1", "mclk2", "mclk3";
185 dma-names = "rx", "tx"; 181 dma-names = "rx", "tx";
186 dmas = <&edma0 0 20>, <&edma0 0 21>; 182 dmas = <&edma0 0 20>, <&edma0 0 21>;
187 big-endian; 183 big-endian;
188 lsb-first; 184 lsb-first;
189 }; 185 };
190 186
191 - | 187 - |
192 #include <dt-bindings/interrupt-controller 188 #include <dt-bindings/interrupt-controller/arm-gic.h>
193 #include <dt-bindings/clock/imx8mm-clock.h 189 #include <dt-bindings/clock/imx8mm-clock.h>
194 sai1: sai@30010000 { 190 sai1: sai@30010000 {
195 compatible = "fsl,imx8mm-sai", "fsl,im 191 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
196 reg = <0x30010000 0x10000>; 192 reg = <0x30010000 0x10000>;
197 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVE 193 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 194 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
199 <&clk IMX8MM_CLK_DUMMY>, 195 <&clk IMX8MM_CLK_DUMMY>,
200 <&clk IMX8MM_CLK_SAI1_ROOT>, 196 <&clk IMX8MM_CLK_SAI1_ROOT>,
201 <&clk IMX8MM_CLK_DUMMY>, <&cl 197 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
202 clock-names = "bus", "mclk0", "mclk1", 198 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
203 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 199 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
204 dma-names = "rx", "tx"; 200 dma-names = "rx", "tx";
205 fsl,dataline = <1 0xff 0xff 2 0xff 0x1 201 fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
206 #sound-dai-cells = <0>; 202 #sound-dai-cells = <0>;
207 }; 203 };
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