1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,s 4 $id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale Synchronous Audio Interface ( 7 title: Freescale Synchronous Audio Interface (SAI).
8 8
9 maintainers: 9 maintainers:
10 - Shengjiu Wang <shengjiu.wang@nxp.com> 10 - Shengjiu Wang <shengjiu.wang@nxp.com>
11 11
12 description: | 12 description: |
13 The SAI is based on I2S module that used com 13 The SAI is based on I2S module that used communicating with audio codecs,
14 which provides a synchronous audio interface 14 which provides a synchronous audio interface that supports fullduplex
15 serial interfaces with frame synchronization 15 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16 codec/DSP interfaces. 16 codec/DSP interfaces.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 oneOf: 20 oneOf:
21 - items: 21 - items:
22 - enum: 22 - enum:
23 - fsl,imx6ul-sai 23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai 24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai 25 - const: fsl,imx6sx-sai
26 26
27 - items: 27 - items:
28 - enum: 28 - enum:
29 - fsl,imx8mm-sai 29 - fsl,imx8mm-sai
30 - fsl,imx8mn-sai 30 - fsl,imx8mn-sai
31 - fsl,imx8mp-sai 31 - fsl,imx8mp-sai
32 - const: fsl,imx8mq-sai 32 - const: fsl,imx8mq-sai
33 33
34 - items: 34 - items:
35 - enum: 35 - enum:
36 - fsl,imx6sx-sai 36 - fsl,imx6sx-sai
37 - fsl,imx7ulp-sai 37 - fsl,imx7ulp-sai
38 - fsl,imx8mq-sai 38 - fsl,imx8mq-sai
39 - fsl,imx8qm-sai 39 - fsl,imx8qm-sai
40 - fsl,imx8ulp-sai 40 - fsl,imx8ulp-sai
41 - fsl,imx93-sai 41 - fsl,imx93-sai
42 - fsl,imx95-sai 42 - fsl,imx95-sai
43 - fsl,vf610-sai 43 - fsl,vf610-sai
44 44
45 reg: 45 reg:
46 maxItems: 1 46 maxItems: 1
47 47
48 clocks: 48 clocks:
49 items: 49 items:
50 - description: The ipg clock for registe 50 - description: The ipg clock for register access
51 - description: master clock source 0 (ob 51 - description: master clock source 0 (obsoleted)
52 - description: master clock source 1 52 - description: master clock source 1
53 - description: master clock source 2 53 - description: master clock source 2
54 - description: master clock source 3 54 - description: master clock source 3
55 - description: PLL clock source for 8kHz 55 - description: PLL clock source for 8kHz series
56 - description: PLL clock source for 11kH 56 - description: PLL clock source for 11kHz series
57 minItems: 4 57 minItems: 4
58 58
59 clock-names: 59 clock-names:
60 oneOf: 60 oneOf:
61 - items: 61 - items:
62 - const: bus 62 - const: bus
63 - const: mclk0 63 - const: mclk0
64 - const: mclk1 64 - const: mclk1
65 - const: mclk2 65 - const: mclk2
66 - const: mclk3 66 - const: mclk3
67 - const: pll8k 67 - const: pll8k
68 - const: pll11k 68 - const: pll11k
69 minItems: 5 69 minItems: 5
70 - items: 70 - items:
71 - const: bus 71 - const: bus
72 - const: mclk1 72 - const: mclk1
73 - const: mclk2 73 - const: mclk2
74 - const: mclk3 74 - const: mclk3
75 - const: pll8k 75 - const: pll8k
76 - const: pll11k 76 - const: pll11k
77 minItems: 4 77 minItems: 4
78 78
79 power-domains: 79 power-domains:
80 maxItems: 1 80 maxItems: 1
81 81
82 dmas: 82 dmas:
83 minItems: 1 83 minItems: 1
84 maxItems: 2 !! 84 items:
>> 85 - description: DMA controller phandle and request line for RX
>> 86 - description: DMA controller phandle and request line for TX
85 87
86 dma-names: 88 dma-names:
87 minItems: 1 89 minItems: 1
88 items: 90 items:
89 - enum: [ rx, tx ] !! 91 - const: rx
90 - const: tx 92 - const: tx
91 93
92 interrupts: 94 interrupts:
93 items: 95 items:
94 - description: receive and transmit inte 96 - description: receive and transmit interrupt
95 97
96 big-endian: 98 big-endian:
97 description: | 99 description: |
98 required if all the SAI registers are bi 100 required if all the SAI registers are big-endian rather than little-endian.
99 type: boolean 101 type: boolean
100 102
101 fsl,dataline: 103 fsl,dataline:
102 $ref: /schemas/types.yaml#/definitions/uin 104 $ref: /schemas/types.yaml#/definitions/uint32-matrix
103 description: | 105 description: |
104 Configure the dataline. It has 3 value f 106 Configure the dataline. It has 3 value for each configuration
105 maxItems: 16 107 maxItems: 16
106 items: 108 items:
107 items: 109 items:
108 - description: format Default(0), I2S( 110 - description: format Default(0), I2S(1) or PDM(2)
109 enum: [0, 1, 2] 111 enum: [0, 1, 2]
110 - description: dataline mask for 'rx' 112 - description: dataline mask for 'rx'
111 - description: dataline mask for 'tx' 113 - description: dataline mask for 'tx'
112 114
113 fsl,sai-mclk-direction-output: 115 fsl,sai-mclk-direction-output:
114 description: SAI will output the SAI MCLK 116 description: SAI will output the SAI MCLK clock.
115 type: boolean 117 type: boolean
116 118
117 fsl,sai-synchronous-rx: 119 fsl,sai-synchronous-rx:
118 description: | 120 description: |
119 SAI will work in the synchronous mode (s 121 SAI will work in the synchronous mode (sync Tx with Rx) which means
120 both the transmitter and the receiver wi 122 both the transmitter and the receiver will send and receive data by
121 following receiver's bit clocks and fram 123 following receiver's bit clocks and frame sync clocks.
122 type: boolean 124 type: boolean
123 125
124 fsl,sai-asynchronous: 126 fsl,sai-asynchronous:
125 description: | 127 description: |
126 SAI will work in the asynchronous mode, 128 SAI will work in the asynchronous mode, which means both transmitter
127 and receiver will send and receive data 129 and receiver will send and receive data by following their own bit clocks
128 and frame sync clocks separately. 130 and frame sync clocks separately.
129 If both fsl,sai-asynchronous and fsl,sai 131 If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
130 default synchronous mode (sync Rx with T 132 default synchronous mode (sync Rx with Tx) will be used, which means both
131 transmitter and receiver will send and r 133 transmitter and receiver will send and receive data by following clocks
132 of transmitter. 134 of transmitter.
133 type: boolean 135 type: boolean
134 136
135 fsl,shared-interrupt: 137 fsl,shared-interrupt:
136 description: Interrupt is shared with othe 138 description: Interrupt is shared with other modules.
137 type: boolean 139 type: boolean
138 140
139 lsb-first: 141 lsb-first:
140 description: | 142 description: |
141 Configures whether the LSB or the MSB is 143 Configures whether the LSB or the MSB is transmitted
142 first for the fifo data. If this propert 144 first for the fifo data. If this property is absent,
143 the MSB is transmitted first as default, 145 the MSB is transmitted first as default, or the LSB
144 is transmitted first. 146 is transmitted first.
145 type: boolean 147 type: boolean
146 148
147 "#sound-dai-cells": 149 "#sound-dai-cells":
148 const: 0 150 const: 0
149 description: optional, some dts node didn' 151 description: optional, some dts node didn't add it.
150 152
151 allOf: 153 allOf:
152 - $ref: dai-common.yaml# 154 - $ref: dai-common.yaml#
153 - if: 155 - if:
154 required: 156 required:
155 - fsl,sai-asynchronous 157 - fsl,sai-asynchronous
156 then: 158 then:
157 properties: 159 properties:
158 fsl,sai-synchronous-rx: false 160 fsl,sai-synchronous-rx: false
159 161
160 required: 162 required:
161 - compatible 163 - compatible
162 - reg 164 - reg
163 - clocks 165 - clocks
164 - clock-names 166 - clock-names
165 - dmas 167 - dmas
166 - dma-names 168 - dma-names
167 - interrupts 169 - interrupts
168 170
169 unevaluatedProperties: false 171 unevaluatedProperties: false
170 172
171 examples: 173 examples:
172 - | 174 - |
173 #include <dt-bindings/interrupt-controller 175 #include <dt-bindings/interrupt-controller/arm-gic.h>
174 #include <dt-bindings/clock/vf610-clock.h> 176 #include <dt-bindings/clock/vf610-clock.h>
175 sai2: sai@40031000 { 177 sai2: sai@40031000 {
176 compatible = "fsl,vf610-sai"; 178 compatible = "fsl,vf610-sai";
177 reg = <0x40031000 0x1000>; 179 reg = <0x40031000 0x1000>;
178 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; 180 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
179 pinctrl-names = "default"; 181 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_sai2_1>; 182 pinctrl-0 = <&pinctrl_sai2_1>;
181 clocks = <&clks VF610_CLK_PLATFORM_BUS 183 clocks = <&clks VF610_CLK_PLATFORM_BUS>,
182 <&clks VF610_CLK_SAI2>, 184 <&clks VF610_CLK_SAI2>,
183 <&clks 0>, <&clks 0>; 185 <&clks 0>, <&clks 0>;
184 clock-names = "bus", "mclk1", "mclk2", 186 clock-names = "bus", "mclk1", "mclk2", "mclk3";
185 dma-names = "rx", "tx"; 187 dma-names = "rx", "tx";
186 dmas = <&edma0 0 20>, <&edma0 0 21>; 188 dmas = <&edma0 0 20>, <&edma0 0 21>;
187 big-endian; 189 big-endian;
188 lsb-first; 190 lsb-first;
189 }; 191 };
190 192
191 - | 193 - |
192 #include <dt-bindings/interrupt-controller 194 #include <dt-bindings/interrupt-controller/arm-gic.h>
193 #include <dt-bindings/clock/imx8mm-clock.h 195 #include <dt-bindings/clock/imx8mm-clock.h>
194 sai1: sai@30010000 { 196 sai1: sai@30010000 {
195 compatible = "fsl,imx8mm-sai", "fsl,im 197 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
196 reg = <0x30010000 0x10000>; 198 reg = <0x30010000 0x10000>;
197 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVE 199 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 200 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
199 <&clk IMX8MM_CLK_DUMMY>, 201 <&clk IMX8MM_CLK_DUMMY>,
200 <&clk IMX8MM_CLK_SAI1_ROOT>, 202 <&clk IMX8MM_CLK_SAI1_ROOT>,
201 <&clk IMX8MM_CLK_DUMMY>, <&cl 203 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
202 clock-names = "bus", "mclk0", "mclk1", 204 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
203 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 205 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
204 dma-names = "rx", "tx"; 206 dma-names = "rx", "tx";
205 fsl,dataline = <1 0xff 0xff 2 0xff 0x1 207 fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
206 #sound-dai-cells = <0>; 208 #sound-dai-cells = <0>;
207 }; 209 };
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