1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,s 4 $id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale Synchronous Audio Interface ( 7 title: Freescale Synchronous Audio Interface (SAI).
8 8
9 maintainers: 9 maintainers:
10 - Shengjiu Wang <shengjiu.wang@nxp.com> 10 - Shengjiu Wang <shengjiu.wang@nxp.com>
11 11
12 description: | 12 description: |
13 The SAI is based on I2S module that used com 13 The SAI is based on I2S module that used communicating with audio codecs,
14 which provides a synchronous audio interface 14 which provides a synchronous audio interface that supports fullduplex
15 serial interfaces with frame synchronization 15 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16 codec/DSP interfaces. 16 codec/DSP interfaces.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 oneOf: 20 oneOf:
21 - items: 21 - items:
22 - enum: 22 - enum:
23 - fsl,imx6ul-sai 23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai 24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai 25 - const: fsl,imx6sx-sai
26 26
27 - items: 27 - items:
28 - enum: 28 - enum:
29 - fsl,imx8mm-sai 29 - fsl,imx8mm-sai
30 - fsl,imx8mn-sai 30 - fsl,imx8mn-sai
31 - fsl,imx8mp-sai 31 - fsl,imx8mp-sai
32 - const: fsl,imx8mq-sai 32 - const: fsl,imx8mq-sai
33 33
34 - items: 34 - items:
35 - enum: 35 - enum:
36 - fsl,imx6sx-sai 36 - fsl,imx6sx-sai
37 - fsl,imx7ulp-sai 37 - fsl,imx7ulp-sai
38 - fsl,imx8mq-sai 38 - fsl,imx8mq-sai
39 - fsl,imx8qm-sai 39 - fsl,imx8qm-sai
40 - fsl,imx8ulp-sai 40 - fsl,imx8ulp-sai
41 - fsl,imx93-sai 41 - fsl,imx93-sai
42 - fsl,imx95-sai 42 - fsl,imx95-sai
43 - fsl,vf610-sai 43 - fsl,vf610-sai
44 44
45 reg: 45 reg:
46 maxItems: 1 46 maxItems: 1
47 47
48 clocks: 48 clocks:
49 items: 49 items:
50 - description: The ipg clock for registe 50 - description: The ipg clock for register access
51 - description: master clock source 0 (ob 51 - description: master clock source 0 (obsoleted)
52 - description: master clock source 1 52 - description: master clock source 1
53 - description: master clock source 2 53 - description: master clock source 2
54 - description: master clock source 3 54 - description: master clock source 3
55 - description: PLL clock source for 8kHz 55 - description: PLL clock source for 8kHz series
56 - description: PLL clock source for 11kH 56 - description: PLL clock source for 11kHz series
57 minItems: 4 57 minItems: 4
58 58
59 clock-names: 59 clock-names:
60 oneOf: 60 oneOf:
61 - items: 61 - items:
62 - const: bus 62 - const: bus
63 - const: mclk0 63 - const: mclk0
64 - const: mclk1 64 - const: mclk1
65 - const: mclk2 65 - const: mclk2
66 - const: mclk3 66 - const: mclk3
67 - const: pll8k 67 - const: pll8k
68 - const: pll11k 68 - const: pll11k
69 minItems: 5 69 minItems: 5
70 - items: 70 - items:
71 - const: bus 71 - const: bus
72 - const: mclk1 72 - const: mclk1
73 - const: mclk2 73 - const: mclk2
74 - const: mclk3 74 - const: mclk3
75 - const: pll8k 75 - const: pll8k
76 - const: pll11k 76 - const: pll11k
77 minItems: 4 77 minItems: 4
78 78
79 power-domains: 79 power-domains:
80 maxItems: 1 80 maxItems: 1
81 81
82 dmas: 82 dmas:
83 minItems: 1 83 minItems: 1
84 maxItems: 2 84 maxItems: 2
85 85
86 dma-names: 86 dma-names:
87 minItems: 1 87 minItems: 1
88 items: 88 items:
89 - enum: [ rx, tx ] 89 - enum: [ rx, tx ]
90 - const: tx 90 - const: tx
91 91
92 interrupts: 92 interrupts:
93 items: 93 items:
94 - description: receive and transmit inte 94 - description: receive and transmit interrupt
95 95
96 big-endian: 96 big-endian:
97 description: | 97 description: |
98 required if all the SAI registers are bi 98 required if all the SAI registers are big-endian rather than little-endian.
99 type: boolean 99 type: boolean
100 100
101 fsl,dataline: 101 fsl,dataline:
102 $ref: /schemas/types.yaml#/definitions/uin 102 $ref: /schemas/types.yaml#/definitions/uint32-matrix
103 description: | 103 description: |
104 Configure the dataline. It has 3 value f 104 Configure the dataline. It has 3 value for each configuration
105 maxItems: 16 105 maxItems: 16
106 items: 106 items:
107 items: 107 items:
108 - description: format Default(0), I2S( 108 - description: format Default(0), I2S(1) or PDM(2)
109 enum: [0, 1, 2] 109 enum: [0, 1, 2]
110 - description: dataline mask for 'rx' 110 - description: dataline mask for 'rx'
111 - description: dataline mask for 'tx' 111 - description: dataline mask for 'tx'
112 112
113 fsl,sai-mclk-direction-output: 113 fsl,sai-mclk-direction-output:
114 description: SAI will output the SAI MCLK 114 description: SAI will output the SAI MCLK clock.
115 type: boolean 115 type: boolean
116 116
117 fsl,sai-synchronous-rx: 117 fsl,sai-synchronous-rx:
118 description: | 118 description: |
119 SAI will work in the synchronous mode (s 119 SAI will work in the synchronous mode (sync Tx with Rx) which means
120 both the transmitter and the receiver wi 120 both the transmitter and the receiver will send and receive data by
121 following receiver's bit clocks and fram 121 following receiver's bit clocks and frame sync clocks.
122 type: boolean 122 type: boolean
123 123
124 fsl,sai-asynchronous: 124 fsl,sai-asynchronous:
125 description: | 125 description: |
126 SAI will work in the asynchronous mode, 126 SAI will work in the asynchronous mode, which means both transmitter
127 and receiver will send and receive data 127 and receiver will send and receive data by following their own bit clocks
128 and frame sync clocks separately. 128 and frame sync clocks separately.
129 If both fsl,sai-asynchronous and fsl,sai 129 If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
130 default synchronous mode (sync Rx with T 130 default synchronous mode (sync Rx with Tx) will be used, which means both
131 transmitter and receiver will send and r 131 transmitter and receiver will send and receive data by following clocks
132 of transmitter. 132 of transmitter.
133 type: boolean 133 type: boolean
134 134
135 fsl,shared-interrupt: 135 fsl,shared-interrupt:
136 description: Interrupt is shared with othe 136 description: Interrupt is shared with other modules.
137 type: boolean 137 type: boolean
138 138
139 lsb-first: 139 lsb-first:
140 description: | 140 description: |
141 Configures whether the LSB or the MSB is 141 Configures whether the LSB or the MSB is transmitted
142 first for the fifo data. If this propert 142 first for the fifo data. If this property is absent,
143 the MSB is transmitted first as default, 143 the MSB is transmitted first as default, or the LSB
144 is transmitted first. 144 is transmitted first.
145 type: boolean 145 type: boolean
146 146
147 "#sound-dai-cells": 147 "#sound-dai-cells":
148 const: 0 148 const: 0
149 description: optional, some dts node didn' 149 description: optional, some dts node didn't add it.
150 150
151 allOf: 151 allOf:
152 - $ref: dai-common.yaml# 152 - $ref: dai-common.yaml#
153 - if: 153 - if:
154 required: 154 required:
155 - fsl,sai-asynchronous 155 - fsl,sai-asynchronous
156 then: 156 then:
157 properties: 157 properties:
158 fsl,sai-synchronous-rx: false 158 fsl,sai-synchronous-rx: false
159 159
160 required: 160 required:
161 - compatible 161 - compatible
162 - reg 162 - reg
163 - clocks 163 - clocks
164 - clock-names 164 - clock-names
165 - dmas 165 - dmas
166 - dma-names 166 - dma-names
167 - interrupts 167 - interrupts
168 168
169 unevaluatedProperties: false 169 unevaluatedProperties: false
170 170
171 examples: 171 examples:
172 - | 172 - |
173 #include <dt-bindings/interrupt-controller 173 #include <dt-bindings/interrupt-controller/arm-gic.h>
174 #include <dt-bindings/clock/vf610-clock.h> 174 #include <dt-bindings/clock/vf610-clock.h>
175 sai2: sai@40031000 { 175 sai2: sai@40031000 {
176 compatible = "fsl,vf610-sai"; 176 compatible = "fsl,vf610-sai";
177 reg = <0x40031000 0x1000>; 177 reg = <0x40031000 0x1000>;
178 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; 178 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
179 pinctrl-names = "default"; 179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_sai2_1>; 180 pinctrl-0 = <&pinctrl_sai2_1>;
181 clocks = <&clks VF610_CLK_PLATFORM_BUS 181 clocks = <&clks VF610_CLK_PLATFORM_BUS>,
182 <&clks VF610_CLK_SAI2>, 182 <&clks VF610_CLK_SAI2>,
183 <&clks 0>, <&clks 0>; 183 <&clks 0>, <&clks 0>;
184 clock-names = "bus", "mclk1", "mclk2", 184 clock-names = "bus", "mclk1", "mclk2", "mclk3";
185 dma-names = "rx", "tx"; 185 dma-names = "rx", "tx";
186 dmas = <&edma0 0 20>, <&edma0 0 21>; 186 dmas = <&edma0 0 20>, <&edma0 0 21>;
187 big-endian; 187 big-endian;
188 lsb-first; 188 lsb-first;
189 }; 189 };
190 190
191 - | 191 - |
192 #include <dt-bindings/interrupt-controller 192 #include <dt-bindings/interrupt-controller/arm-gic.h>
193 #include <dt-bindings/clock/imx8mm-clock.h 193 #include <dt-bindings/clock/imx8mm-clock.h>
194 sai1: sai@30010000 { 194 sai1: sai@30010000 {
195 compatible = "fsl,imx8mm-sai", "fsl,im 195 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
196 reg = <0x30010000 0x10000>; 196 reg = <0x30010000 0x10000>;
197 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVE 197 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 198 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
199 <&clk IMX8MM_CLK_DUMMY>, 199 <&clk IMX8MM_CLK_DUMMY>,
200 <&clk IMX8MM_CLK_SAI1_ROOT>, 200 <&clk IMX8MM_CLK_SAI1_ROOT>,
201 <&clk IMX8MM_CLK_DUMMY>, <&cl 201 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
202 clock-names = "bus", "mclk0", "mclk1", 202 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
203 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 203 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
204 dma-names = "rx", "tx"; 204 dma-names = "rx", "tx";
205 fsl,dataline = <1 0xff 0xff 2 0xff 0x1 205 fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
206 #sound-dai-cells = <0>; 206 #sound-dai-cells = <0>;
207 }; 207 };
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