1 Mediatek AFE PCM controller for mt8183 1 Mediatek AFE PCM controller for mt8183
2 2
3 Required properties: 3 Required properties:
4 - compatible = "mediatek,mt68183-audio"; 4 - compatible = "mediatek,mt68183-audio";
5 - reg: register location and size 5 - reg: register location and size
6 - interrupts: should contain AFE interrupt 6 - interrupts: should contain AFE interrupt
7 - resets: Must contain an entry for each entry 7 - resets: Must contain an entry for each entry in reset-names
8 See ../reset/reset.txt for details. 8 See ../reset/reset.txt for details.
9 - reset-names: should have these reset names: 9 - reset-names: should have these reset names:
10 "audiosys"; 10 "audiosys";
11 - power-domains: should define the power domai 11 - power-domains: should define the power domain
12 - clocks: Must contain an entry for each entry 12 - clocks: Must contain an entry for each entry in clock-names
13 - clock-names: should have these clock names: 13 - clock-names: should have these clock names:
14 "infra_sys_audio_clk", 14 "infra_sys_audio_clk",
15 "mtkaif_26m_clk", 15 "mtkaif_26m_clk",
16 "top_mux_audio", 16 "top_mux_audio",
17 "top_mux_aud_intbus", 17 "top_mux_aud_intbus",
18 "top_sys_pll3_d4", 18 "top_sys_pll3_d4",
19 "top_clk26m_clk"; 19 "top_clk26m_clk";
20 20
21 Example: 21 Example:
22 22
23 afe: mt8183-afe-pcm@11220000 { 23 afe: mt8183-afe-pcm@11220000 {
24 compatible = "mediatek,mt8183- 24 compatible = "mediatek,mt8183-audio";
25 reg = <0 0x11220000 0 0x1000>; 25 reg = <0 0x11220000 0 0x1000>;
26 interrupts = <GIC_SPI 161 IRQ_ 26 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
27 resets = <&watchdog MT8183_TOP 27 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
28 reset-names = "audiosys"; 28 reset-names = "audiosys";
29 power-domains = <&scpsys MT818 29 power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>;
30 clocks = <&infrasys CLK_INFRA_ 30 clocks = <&infrasys CLK_INFRA_AUDIO>,
31 <&infrasys CLK_INFRA_ 31 <&infrasys CLK_INFRA_AUDIO_26M_BCLK>,
32 <&topckgen CLK_TOP_MU 32 <&topckgen CLK_TOP_MUX_AUDIO>,
33 <&topckgen CLK_TOP_MU 33 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
34 <&topckgen CLK_TOP_SY 34 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
35 <&clk26m>; 35 <&clk26m>;
36 clock-names = "infra_sys_audio 36 clock-names = "infra_sys_audio_clk",
37 "mtkaif_26m_clk" 37 "mtkaif_26m_clk",
38 "top_mux_audio", 38 "top_mux_audio",
39 "top_mux_aud_int 39 "top_mux_aud_intbus",
40 "top_sys_pll_d2_ 40 "top_sys_pll_d2_d4",
41 "top_clk26m_clk" 41 "top_clk26m_clk";
42 }; 42 };
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