1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/mt818 4 $id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Mediatek AFE PCM controller for mt8186 7 title: Mediatek AFE PCM controller for mt8186
8 8
9 maintainers: 9 maintainers:
10 - Jiaxin Yu <jiaxin.yu@mediatek.com> 10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
11 11
12 properties: 12 properties:
13 compatible: 13 compatible:
14 const: mediatek,mt8186-sound 14 const: mediatek,mt8186-sound
15 15
16 reg: 16 reg:
17 maxItems: 1 17 maxItems: 1
18 18
19 interrupts: 19 interrupts:
20 maxItems: 1 20 maxItems: 1
21 21
22 resets: 22 resets:
23 maxItems: 1 23 maxItems: 1
24 24
25 reset-names: 25 reset-names:
26 const: audiosys 26 const: audiosys
27 27
28 mediatek,apmixedsys: 28 mediatek,apmixedsys:
29 $ref: /schemas/types.yaml#/definitions/pha 29 $ref: /schemas/types.yaml#/definitions/phandle
30 description: The phandle of the mediatek a 30 description: The phandle of the mediatek apmixedsys controller
31 31
32 mediatek,infracfg: 32 mediatek,infracfg:
33 $ref: /schemas/types.yaml#/definitions/pha 33 $ref: /schemas/types.yaml#/definitions/phandle
34 description: The phandle of the mediatek i 34 description: The phandle of the mediatek infracfg controller
35 35
36 mediatek,topckgen: 36 mediatek,topckgen:
37 $ref: /schemas/types.yaml#/definitions/pha 37 $ref: /schemas/types.yaml#/definitions/phandle
38 description: The phandle of the mediatek t 38 description: The phandle of the mediatek topckgen controller
39 39
40 clocks: 40 clocks:
41 items: 41 items:
42 - description: audio infra sys clock 42 - description: audio infra sys clock
43 - description: audio infra 26M clock 43 - description: audio infra 26M clock
44 - description: audio top mux 44 - description: audio top mux
45 - description: audio intbus mux 45 - description: audio intbus mux
46 - description: mainpll 136.5M clock 46 - description: mainpll 136.5M clock
47 - description: faud1 mux 47 - description: faud1 mux
48 - description: apll1 clock 48 - description: apll1 clock
49 - description: faud2 mux 49 - description: faud2 mux
50 - description: apll2 clock 50 - description: apll2 clock
51 - description: audio engen1 mux 51 - description: audio engen1 mux
52 - description: apll1_d8 22.5792M clock 52 - description: apll1_d8 22.5792M clock
53 - description: audio engen2 mux 53 - description: audio engen2 mux
54 - description: apll2_d8 24.576M clock 54 - description: apll2_d8 24.576M clock
55 - description: i2s0 mclk mux 55 - description: i2s0 mclk mux
56 - description: i2s1 mclk mux 56 - description: i2s1 mclk mux
57 - description: i2s2 mclk mux 57 - description: i2s2 mclk mux
58 - description: i2s4 mclk mux 58 - description: i2s4 mclk mux
59 - description: tdm mclk mux 59 - description: tdm mclk mux
60 - description: i2s0_mck divider 60 - description: i2s0_mck divider
61 - description: i2s1_mck divider 61 - description: i2s1_mck divider
62 - description: i2s2_mck divider 62 - description: i2s2_mck divider
63 - description: i2s4_mck divider 63 - description: i2s4_mck divider
64 - description: tdm_mck divider 64 - description: tdm_mck divider
65 - description: audio hires mux 65 - description: audio hires mux
66 - description: 26M clock 66 - description: 26M clock
67 67
68 clock-names: 68 clock-names:
69 items: 69 items:
70 - const: aud_infra_clk 70 - const: aud_infra_clk
71 - const: mtkaif_26m_clk 71 - const: mtkaif_26m_clk
72 - const: top_mux_audio 72 - const: top_mux_audio
73 - const: top_mux_audio_int 73 - const: top_mux_audio_int
74 - const: top_mainpll_d2_d4 74 - const: top_mainpll_d2_d4
75 - const: top_mux_aud_1 75 - const: top_mux_aud_1
76 - const: top_apll1_ck 76 - const: top_apll1_ck
77 - const: top_mux_aud_2 77 - const: top_mux_aud_2
78 - const: top_apll2_ck 78 - const: top_apll2_ck
79 - const: top_mux_aud_eng1 79 - const: top_mux_aud_eng1
80 - const: top_apll1_d8 80 - const: top_apll1_d8
81 - const: top_mux_aud_eng2 81 - const: top_mux_aud_eng2
82 - const: top_apll2_d8 82 - const: top_apll2_d8
83 - const: top_i2s0_m_sel 83 - const: top_i2s0_m_sel
84 - const: top_i2s1_m_sel 84 - const: top_i2s1_m_sel
85 - const: top_i2s2_m_sel 85 - const: top_i2s2_m_sel
86 - const: top_i2s4_m_sel 86 - const: top_i2s4_m_sel
87 - const: top_tdm_m_sel 87 - const: top_tdm_m_sel
88 - const: top_apll12_div0 88 - const: top_apll12_div0
89 - const: top_apll12_div1 89 - const: top_apll12_div1
90 - const: top_apll12_div2 90 - const: top_apll12_div2
91 - const: top_apll12_div4 91 - const: top_apll12_div4
92 - const: top_apll12_div_tdm 92 - const: top_apll12_div_tdm
93 - const: top_mux_audio_h 93 - const: top_mux_audio_h
94 - const: top_clk26m_clk 94 - const: top_clk26m_clk
95 95
96 required: 96 required:
97 - compatible 97 - compatible
98 - interrupts 98 - interrupts
99 - resets 99 - resets
100 - reset-names 100 - reset-names
101 - mediatek,apmixedsys 101 - mediatek,apmixedsys
102 - mediatek,infracfg 102 - mediatek,infracfg
103 - mediatek,topckgen 103 - mediatek,topckgen
104 - clocks 104 - clocks
105 - clock-names 105 - clock-names
106 106
107 additionalProperties: false 107 additionalProperties: false
108 108
109 examples: 109 examples:
110 - | 110 - |
111 #include <dt-bindings/interrupt-controller 111 #include <dt-bindings/interrupt-controller/arm-gic.h>
112 #include <dt-bindings/interrupt-controller 112 #include <dt-bindings/interrupt-controller/irq.h>
113 113
114 afe: mt8186-afe-pcm@11210000 { 114 afe: mt8186-afe-pcm@11210000 {
115 compatible = "mediatek,mt8186-sound"; 115 compatible = "mediatek,mt8186-sound";
116 reg = <0x11210000 0x2000>; 116 reg = <0x11210000 0x2000>;
117 interrupts = <GIC_SPI 169 IRQ_TYPE_LEV 117 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
118 resets = <&watchdog 17>; //MT8186_TOPR 118 resets = <&watchdog 17>; //MT8186_TOPRGU_AUDIO_SW_RST
119 reset-names = "audiosys"; 119 reset-names = "audiosys";
120 mediatek,apmixedsys = <&apmixedsys>; 120 mediatek,apmixedsys = <&apmixedsys>;
121 mediatek,infracfg = <&infracfg>; 121 mediatek,infracfg = <&infracfg>;
122 mediatek,topckgen = <&topckgen>; 122 mediatek,topckgen = <&topckgen>;
123 clocks = <&infracfg_ao 44>, //CLK_INFR 123 clocks = <&infracfg_ao 44>, //CLK_INFRA_AO_AUDIO
124 <&infracfg_ao 54>, //CLK_INFR 124 <&infracfg_ao 54>, //CLK_INFRA_AO_AUDIO_26M_BCLK
125 <&topckgen 15>, //CLK_TOP_AUD 125 <&topckgen 15>, //CLK_TOP_AUDIO
126 <&topckgen 16>, //CLK_TOP_AUD 126 <&topckgen 16>, //CLK_TOP_AUD_INTBUS
127 <&topckgen 70>, //CLK_TOP_MAI 127 <&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4
128 <&topckgen 17>, //CLK_TOP_AUD 128 <&topckgen 17>, //CLK_TOP_AUD_1
129 <&apmixedsys 12>, //CLK_APMIX 129 <&apmixedsys 12>, //CLK_APMIXED_APLL1
130 <&topckgen 18>, //CLK_TOP_AUD 130 <&topckgen 18>, //CLK_TOP_AUD_2
131 <&apmixedsys 13>, //CLK_APMIX 131 <&apmixedsys 13>, //CLK_APMIXED_APLL2
132 <&topckgen 19>, //CLK_TOP_AUD 132 <&topckgen 19>, //CLK_TOP_AUD_ENGEN1
133 <&topckgen 101>, //CLK_TOP_AP 133 <&topckgen 101>, //CLK_TOP_APLL1_D8
134 <&topckgen 20>, //CLK_TOP_AUD 134 <&topckgen 20>, //CLK_TOP_AUD_ENGEN2
135 <&topckgen 104>, //CLK_TOP_AP 135 <&topckgen 104>, //CLK_TOP_APLL2_D8
136 <&topckgen 63>, //CLK_TOP_APL 136 <&topckgen 63>, //CLK_TOP_APLL_I2S0_MCK_SEL
137 <&topckgen 64>, //CLK_TOP_APL 137 <&topckgen 64>, //CLK_TOP_APLL_I2S1_MCK_SEL
138 <&topckgen 65>, //CLK_TOP_APL 138 <&topckgen 65>, //CLK_TOP_APLL_I2S2_MCK_SEL
139 <&topckgen 66>, //CLK_TOP_APL 139 <&topckgen 66>, //CLK_TOP_APLL_I2S4_MCK_SEL
140 <&topckgen 67>, //CLK_TOP_APL 140 <&topckgen 67>, //CLK_TOP_APLL_TDMOUT_MCK_SEL
141 <&topckgen 131>, //CLK_TOP_AP 141 <&topckgen 131>, //CLK_TOP_APLL12_CK_DIV0
142 <&topckgen 132>, //CLK_TOP_AP 142 <&topckgen 132>, //CLK_TOP_APLL12_CK_DIV1
143 <&topckgen 133>, //CLK_TOP_AP 143 <&topckgen 133>, //CLK_TOP_APLL12_CK_DIV2
144 <&topckgen 134>, //CLK_TOP_AP 144 <&topckgen 134>, //CLK_TOP_APLL12_CK_DIV4
145 <&topckgen 135>, //CLK_TOP_AP 145 <&topckgen 135>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M
146 <&topckgen 44>, //CLK_TOP_AUD 146 <&topckgen 44>, //CLK_TOP_AUDIO_H
147 <&clk26m>; 147 <&clk26m>;
148 clock-names = "aud_infra_clk", 148 clock-names = "aud_infra_clk",
149 "mtkaif_26m_clk", 149 "mtkaif_26m_clk",
150 "top_mux_audio", 150 "top_mux_audio",
151 "top_mux_audio_int", 151 "top_mux_audio_int",
152 "top_mainpll_d2_d4", 152 "top_mainpll_d2_d4",
153 "top_mux_aud_1", 153 "top_mux_aud_1",
154 "top_apll1_ck", 154 "top_apll1_ck",
155 "top_mux_aud_2", 155 "top_mux_aud_2",
156 "top_apll2_ck", 156 "top_apll2_ck",
157 "top_mux_aud_eng1", 157 "top_mux_aud_eng1",
158 "top_apll1_d8", 158 "top_apll1_d8",
159 "top_mux_aud_eng2", 159 "top_mux_aud_eng2",
160 "top_apll2_d8", 160 "top_apll2_d8",
161 "top_i2s0_m_sel", 161 "top_i2s0_m_sel",
162 "top_i2s1_m_sel", 162 "top_i2s1_m_sel",
163 "top_i2s2_m_sel", 163 "top_i2s2_m_sel",
164 "top_i2s4_m_sel", 164 "top_i2s4_m_sel",
165 "top_tdm_m_sel", 165 "top_tdm_m_sel",
166 "top_apll12_div0", 166 "top_apll12_div0",
167 "top_apll12_div1", 167 "top_apll12_div1",
168 "top_apll12_div2", 168 "top_apll12_div2",
169 "top_apll12_div4", 169 "top_apll12_div4",
170 "top_apll12_div_tdm", 170 "top_apll12_div_tdm",
171 "top_mux_audio_h", 171 "top_mux_audio_h",
172 "top_clk26m_clk"; 172 "top_clk26m_clk";
173 }; 173 };
174 174
175 ... 175 ...
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