1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/nvidi 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Audio Graph based Tegra sound card driv 7 title: Audio Graph based Tegra sound card driver
8 8
9 description: | 9 description: |
10 This is based on generic audio graph card dr 10 This is based on generic audio graph card driver along with additional
11 customizations for Tegra platforms. It uses 11 customizations for Tegra platforms. It uses the same bindings with
12 additional standard clock DT bindings requir 12 additional standard clock DT bindings required for Tegra.
13 13
14 maintainers: 14 maintainers:
15 - Jon Hunter <jonathanh@nvidia.com> 15 - Jon Hunter <jonathanh@nvidia.com>
16 - Sameer Pujar <spujar@nvidia.com> 16 - Sameer Pujar <spujar@nvidia.com>
17 17
18 allOf: 18 allOf:
19 - $ref: audio-graph.yaml# 19 - $ref: audio-graph.yaml#
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 enum: 23 enum:
24 - nvidia,tegra210-audio-graph-card 24 - nvidia,tegra210-audio-graph-card
25 - nvidia,tegra186-audio-graph-card 25 - nvidia,tegra186-audio-graph-card
26 26
27 clocks: 27 clocks:
28 minItems: 2 28 minItems: 2
29 29
30 clock-names: 30 clock-names:
>> 31 minItems: 2
31 items: 32 items:
32 - const: pll_a 33 - const: pll_a
33 - const: plla_out0 34 - const: plla_out0
34 35
35 assigned-clocks: 36 assigned-clocks:
36 minItems: 1 37 minItems: 1
37 maxItems: 3 38 maxItems: 3
38 39
39 assigned-clock-parents: 40 assigned-clock-parents:
40 minItems: 1 41 minItems: 1
41 maxItems: 3 42 maxItems: 3
42 43
43 assigned-clock-rates: 44 assigned-clock-rates:
44 minItems: 1 45 minItems: 1
45 maxItems: 3 46 maxItems: 3
46 <<
47 interconnects: <<
48 items: <<
49 - description: APE read memory client <<
50 - description: APE write memory client <<
51 <<
52 interconnect-names: <<
53 items: <<
54 - const: dma-mem # read <<
55 - const: write <<
56 47
57 iommus: 48 iommus:
58 maxItems: 1 49 maxItems: 1
59 50
60 required: 51 required:
61 - clocks 52 - clocks
62 - clock-names 53 - clock-names
63 - assigned-clocks 54 - assigned-clocks
64 - assigned-clock-parents 55 - assigned-clock-parents
65 56
66 unevaluatedProperties: false 57 unevaluatedProperties: false
67 58
68 examples: 59 examples:
69 - | 60 - |
70 #include<dt-bindings/clock/tegra210-car.h> 61 #include<dt-bindings/clock/tegra210-car.h>
71 62
72 tegra_sound { 63 tegra_sound {
73 compatible = "nvidia,tegra210-audio-gr 64 compatible = "nvidia,tegra210-audio-graph-card";
74 65
75 clocks = <&tegra_car TEGRA210_CLK_PLL_ 66 clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
76 <&tegra_car TEGRA210_CLK_PLL_ 67 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
77 clock-names = "pll_a", "plla_out0"; 68 clock-names = "pll_a", "plla_out0";
78 69
79 assigned-clocks = <&tegra_car TEGRA210 70 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
80 <&tegra_car TEGRA210 71 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
81 <&tegra_car TEGRA210 72 <&tegra_car TEGRA210_CLK_EXTERN1>;
82 assigned-clock-parents = <0>, <0>, <&t 73 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
83 assigned-clock-rates = <368640000>, <4 74 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
84 75
85 dais = /* FE */ 76 dais = /* FE */
86 <&admaif1_port>, 77 <&admaif1_port>,
87 /* Router */ 78 /* Router */
88 <&xbar_i2s1_port>, 79 <&xbar_i2s1_port>,
89 /* I/O DAP Ports */ 80 /* I/O DAP Ports */
90 <&i2s1_port>; 81 <&i2s1_port>;
91 82
92 label = "jetson-tx1-ape"; 83 label = "jetson-tx1-ape";
93 }; 84 };
94 85
95 // The ports are defined for AHUB and its 86 // The ports are defined for AHUB and its child devices.
96 ahub@702d0800 { 87 ahub@702d0800 {
97 compatible = "nvidia,tegra210-ahub"; 88 compatible = "nvidia,tegra210-ahub";
98 reg = <0x702d0800 0x800>; 89 reg = <0x702d0800 0x800>;
99 clocks = <&tegra_car TEGRA210_CLK_D_AU 90 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
100 clock-names = "ahub"; 91 clock-names = "ahub";
101 assigned-clocks = <&tegra_car TEGRA210 92 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
102 assigned-clock-parents = <&tegra_car T 93 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
103 #address-cells = <1>; 94 #address-cells = <1>;
104 #size-cells = <1>; 95 #size-cells = <1>;
105 ranges = <0x702d0000 0x702d0000 0x0000 96 ranges = <0x702d0000 0x702d0000 0x0000e400>;
106 97
107 ports { 98 ports {
108 #address-cells = <1>; 99 #address-cells = <1>;
109 #size-cells = <0>; 100 #size-cells = <0>;
110 101
111 port@0 { 102 port@0 {
112 reg = <0x0>; 103 reg = <0x0>;
113 xbar_admaif1_ep: endpoint { 104 xbar_admaif1_ep: endpoint {
114 remote-endpoint = <&admaif 105 remote-endpoint = <&admaif1_ep>;
115 }; 106 };
116 }; 107 };
117 108
118 // ... 109 // ...
119 110
120 xbar_i2s1_port: port@a { 111 xbar_i2s1_port: port@a {
121 reg = <0xa>; 112 reg = <0xa>;
122 xbar_i2s1_ep: endpoint { 113 xbar_i2s1_ep: endpoint {
123 remote-endpoint = <&i2s1_c 114 remote-endpoint = <&i2s1_cif_ep>;
124 }; 115 };
125 }; 116 };
126 }; 117 };
127 118
128 admaif@702d0000 { 119 admaif@702d0000 {
129 compatible = "nvidia,tegra210-adma 120 compatible = "nvidia,tegra210-admaif";
130 reg = <0x702d0000 0x800>; 121 reg = <0x702d0000 0x800>;
131 dmas = <&adma 1>, <&adma 1>, 122 dmas = <&adma 1>, <&adma 1>,
132 <&adma 2>, <&adma 2>, 123 <&adma 2>, <&adma 2>,
133 <&adma 3>, <&adma 3>, 124 <&adma 3>, <&adma 3>,
134 <&adma 4>, <&adma 4>, 125 <&adma 4>, <&adma 4>,
135 <&adma 5>, <&adma 5>, 126 <&adma 5>, <&adma 5>,
136 <&adma 6>, <&adma 6>, 127 <&adma 6>, <&adma 6>,
137 <&adma 7>, <&adma 7>, 128 <&adma 7>, <&adma 7>,
138 <&adma 8>, <&adma 8>, 129 <&adma 8>, <&adma 8>,
139 <&adma 9>, <&adma 9>, 130 <&adma 9>, <&adma 9>,
140 <&adma 10>, <&adma 10>; 131 <&adma 10>, <&adma 10>;
141 dma-names = "rx1", "tx1", 132 dma-names = "rx1", "tx1",
142 "rx2", "tx2", 133 "rx2", "tx2",
143 "rx3", "tx3", 134 "rx3", "tx3",
144 "rx4", "tx4", 135 "rx4", "tx4",
145 "rx5", "tx5", 136 "rx5", "tx5",
146 "rx6", "tx6", 137 "rx6", "tx6",
147 "rx7", "tx7", 138 "rx7", "tx7",
148 "rx8", "tx8", 139 "rx8", "tx8",
149 "rx9", "tx9", 140 "rx9", "tx9",
150 "rx10", "tx10"; 141 "rx10", "tx10";
151 142
152 ports { 143 ports {
153 #address-cells = <1>; 144 #address-cells = <1>;
154 #size-cells = <0>; 145 #size-cells = <0>;
155 146
156 admaif1_port: port@0 { 147 admaif1_port: port@0 {
157 reg = <0x0>; 148 reg = <0x0>;
158 admaif1_ep: endpoint { 149 admaif1_ep: endpoint {
159 remote-endpoint = <&xb 150 remote-endpoint = <&xbar_admaif1_ep>;
160 }; 151 };
161 }; 152 };
162 153
163 // More ADMAIF ports to follow 154 // More ADMAIF ports to follow
164 }; 155 };
165 }; 156 };
166 157
167 i2s@702d1000 { 158 i2s@702d1000 {
168 compatible = "nvidia,tegra210-i2s" 159 compatible = "nvidia,tegra210-i2s";
169 clocks = <&tegra_car TEGRA210_CLK_ 160 clocks = <&tegra_car TEGRA210_CLK_I2S0>;
170 clock-names = "i2s"; 161 clock-names = "i2s";
171 assigned-clocks = <&tegra_car TEGR 162 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
172 assigned-clock-parents = <&tegra_c 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
173 assigned-clock-rates = <1536000>; 164 assigned-clock-rates = <1536000>;
174 reg = <0x702d1000 0x100>; 165 reg = <0x702d1000 0x100>;
175 166
176 ports { 167 ports {
177 #address-cells = <1>; 168 #address-cells = <1>;
178 #size-cells = <0>; 169 #size-cells = <0>;
179 170
180 port@0 { 171 port@0 {
181 reg = <0x0>; 172 reg = <0x0>;
182 173
183 i2s1_cif_ep: endpoint { 174 i2s1_cif_ep: endpoint {
184 remote-endpoint = <&xb 175 remote-endpoint = <&xbar_i2s1_ep>;
185 }; 176 };
186 }; 177 };
187 178
188 i2s1_port: port@1 { 179 i2s1_port: port@1 {
189 reg = <0x1>; 180 reg = <0x1>;
190 181
191 i2s1_dap: endpoint { 182 i2s1_dap: endpoint {
192 dai-format = "i2s"; 183 dai-format = "i2s";
193 }; 184 };
194 }; 185 };
195 }; 186 };
196 }; 187 };
197 }; 188 };
198 189
199 ... 190 ...
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