1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/nvidi 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Audio Graph based Tegra sound card driv 7 title: Audio Graph based Tegra sound card driver
8 8
9 description: | 9 description: |
10 This is based on generic audio graph card dr 10 This is based on generic audio graph card driver along with additional
11 customizations for Tegra platforms. It uses 11 customizations for Tegra platforms. It uses the same bindings with
12 additional standard clock DT bindings requir 12 additional standard clock DT bindings required for Tegra.
13 13
14 maintainers: 14 maintainers:
15 - Jon Hunter <jonathanh@nvidia.com> 15 - Jon Hunter <jonathanh@nvidia.com>
16 - Sameer Pujar <spujar@nvidia.com> 16 - Sameer Pujar <spujar@nvidia.com>
17 17
18 allOf: 18 allOf:
19 - $ref: audio-graph.yaml# 19 - $ref: audio-graph.yaml#
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 enum: 23 enum:
24 - nvidia,tegra210-audio-graph-card 24 - nvidia,tegra210-audio-graph-card
25 - nvidia,tegra186-audio-graph-card 25 - nvidia,tegra186-audio-graph-card
26 26
27 clocks: 27 clocks:
28 minItems: 2 28 minItems: 2
29 29
30 clock-names: 30 clock-names:
31 items: 31 items:
32 - const: pll_a 32 - const: pll_a
33 - const: plla_out0 33 - const: plla_out0
34 34
35 assigned-clocks: 35 assigned-clocks:
36 minItems: 1 36 minItems: 1
37 maxItems: 3 37 maxItems: 3
38 38
39 assigned-clock-parents: 39 assigned-clock-parents:
40 minItems: 1 40 minItems: 1
41 maxItems: 3 41 maxItems: 3
42 42
43 assigned-clock-rates: 43 assigned-clock-rates:
44 minItems: 1 44 minItems: 1
45 maxItems: 3 45 maxItems: 3
46 46
47 interconnects: 47 interconnects:
48 items: 48 items:
49 - description: APE read memory client 49 - description: APE read memory client
50 - description: APE write memory client 50 - description: APE write memory client
51 51
52 interconnect-names: 52 interconnect-names:
53 items: 53 items:
54 - const: dma-mem # read 54 - const: dma-mem # read
55 - const: write 55 - const: write
56 56
57 iommus: 57 iommus:
58 maxItems: 1 58 maxItems: 1
59 59
60 required: 60 required:
61 - clocks 61 - clocks
62 - clock-names 62 - clock-names
63 - assigned-clocks 63 - assigned-clocks
64 - assigned-clock-parents 64 - assigned-clock-parents
65 65
66 unevaluatedProperties: false 66 unevaluatedProperties: false
67 67
68 examples: 68 examples:
69 - | 69 - |
70 #include<dt-bindings/clock/tegra210-car.h> 70 #include<dt-bindings/clock/tegra210-car.h>
71 71
72 tegra_sound { 72 tegra_sound {
73 compatible = "nvidia,tegra210-audio-gr 73 compatible = "nvidia,tegra210-audio-graph-card";
74 74
75 clocks = <&tegra_car TEGRA210_CLK_PLL_ 75 clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
76 <&tegra_car TEGRA210_CLK_PLL_ 76 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
77 clock-names = "pll_a", "plla_out0"; 77 clock-names = "pll_a", "plla_out0";
78 78
79 assigned-clocks = <&tegra_car TEGRA210 79 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
80 <&tegra_car TEGRA210 80 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
81 <&tegra_car TEGRA210 81 <&tegra_car TEGRA210_CLK_EXTERN1>;
82 assigned-clock-parents = <0>, <0>, <&t 82 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
83 assigned-clock-rates = <368640000>, <4 83 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
84 84
85 dais = /* FE */ 85 dais = /* FE */
86 <&admaif1_port>, 86 <&admaif1_port>,
87 /* Router */ 87 /* Router */
88 <&xbar_i2s1_port>, 88 <&xbar_i2s1_port>,
89 /* I/O DAP Ports */ 89 /* I/O DAP Ports */
90 <&i2s1_port>; 90 <&i2s1_port>;
91 91
92 label = "jetson-tx1-ape"; 92 label = "jetson-tx1-ape";
93 }; 93 };
94 94
95 // The ports are defined for AHUB and its 95 // The ports are defined for AHUB and its child devices.
96 ahub@702d0800 { 96 ahub@702d0800 {
97 compatible = "nvidia,tegra210-ahub"; 97 compatible = "nvidia,tegra210-ahub";
98 reg = <0x702d0800 0x800>; 98 reg = <0x702d0800 0x800>;
99 clocks = <&tegra_car TEGRA210_CLK_D_AU 99 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
100 clock-names = "ahub"; 100 clock-names = "ahub";
101 assigned-clocks = <&tegra_car TEGRA210 101 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
102 assigned-clock-parents = <&tegra_car T 102 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
103 #address-cells = <1>; 103 #address-cells = <1>;
104 #size-cells = <1>; 104 #size-cells = <1>;
105 ranges = <0x702d0000 0x702d0000 0x0000 105 ranges = <0x702d0000 0x702d0000 0x0000e400>;
106 106
107 ports { 107 ports {
108 #address-cells = <1>; 108 #address-cells = <1>;
109 #size-cells = <0>; 109 #size-cells = <0>;
110 110
111 port@0 { 111 port@0 {
112 reg = <0x0>; 112 reg = <0x0>;
113 xbar_admaif1_ep: endpoint { 113 xbar_admaif1_ep: endpoint {
114 remote-endpoint = <&admaif 114 remote-endpoint = <&admaif1_ep>;
115 }; 115 };
116 }; 116 };
117 117
118 // ... 118 // ...
119 119
120 xbar_i2s1_port: port@a { 120 xbar_i2s1_port: port@a {
121 reg = <0xa>; 121 reg = <0xa>;
122 xbar_i2s1_ep: endpoint { 122 xbar_i2s1_ep: endpoint {
123 remote-endpoint = <&i2s1_c 123 remote-endpoint = <&i2s1_cif_ep>;
124 }; 124 };
125 }; 125 };
126 }; 126 };
127 127
128 admaif@702d0000 { 128 admaif@702d0000 {
129 compatible = "nvidia,tegra210-adma 129 compatible = "nvidia,tegra210-admaif";
130 reg = <0x702d0000 0x800>; 130 reg = <0x702d0000 0x800>;
131 dmas = <&adma 1>, <&adma 1>, 131 dmas = <&adma 1>, <&adma 1>,
132 <&adma 2>, <&adma 2>, 132 <&adma 2>, <&adma 2>,
133 <&adma 3>, <&adma 3>, 133 <&adma 3>, <&adma 3>,
134 <&adma 4>, <&adma 4>, 134 <&adma 4>, <&adma 4>,
135 <&adma 5>, <&adma 5>, 135 <&adma 5>, <&adma 5>,
136 <&adma 6>, <&adma 6>, 136 <&adma 6>, <&adma 6>,
137 <&adma 7>, <&adma 7>, 137 <&adma 7>, <&adma 7>,
138 <&adma 8>, <&adma 8>, 138 <&adma 8>, <&adma 8>,
139 <&adma 9>, <&adma 9>, 139 <&adma 9>, <&adma 9>,
140 <&adma 10>, <&adma 10>; 140 <&adma 10>, <&adma 10>;
141 dma-names = "rx1", "tx1", 141 dma-names = "rx1", "tx1",
142 "rx2", "tx2", 142 "rx2", "tx2",
143 "rx3", "tx3", 143 "rx3", "tx3",
144 "rx4", "tx4", 144 "rx4", "tx4",
145 "rx5", "tx5", 145 "rx5", "tx5",
146 "rx6", "tx6", 146 "rx6", "tx6",
147 "rx7", "tx7", 147 "rx7", "tx7",
148 "rx8", "tx8", 148 "rx8", "tx8",
149 "rx9", "tx9", 149 "rx9", "tx9",
150 "rx10", "tx10"; 150 "rx10", "tx10";
151 151
152 ports { 152 ports {
153 #address-cells = <1>; 153 #address-cells = <1>;
154 #size-cells = <0>; 154 #size-cells = <0>;
155 155
156 admaif1_port: port@0 { 156 admaif1_port: port@0 {
157 reg = <0x0>; 157 reg = <0x0>;
158 admaif1_ep: endpoint { 158 admaif1_ep: endpoint {
159 remote-endpoint = <&xb 159 remote-endpoint = <&xbar_admaif1_ep>;
160 }; 160 };
161 }; 161 };
162 162
163 // More ADMAIF ports to follow 163 // More ADMAIF ports to follow
164 }; 164 };
165 }; 165 };
166 166
167 i2s@702d1000 { 167 i2s@702d1000 {
168 compatible = "nvidia,tegra210-i2s" 168 compatible = "nvidia,tegra210-i2s";
169 clocks = <&tegra_car TEGRA210_CLK_ 169 clocks = <&tegra_car TEGRA210_CLK_I2S0>;
170 clock-names = "i2s"; 170 clock-names = "i2s";
171 assigned-clocks = <&tegra_car TEGR 171 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
172 assigned-clock-parents = <&tegra_c 172 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
173 assigned-clock-rates = <1536000>; 173 assigned-clock-rates = <1536000>;
174 reg = <0x702d1000 0x100>; 174 reg = <0x702d1000 0x100>;
175 175
176 ports { 176 ports {
177 #address-cells = <1>; 177 #address-cells = <1>;
178 #size-cells = <0>; 178 #size-cells = <0>;
179 179
180 port@0 { 180 port@0 {
181 reg = <0x0>; 181 reg = <0x0>;
182 182
183 i2s1_cif_ep: endpoint { 183 i2s1_cif_ep: endpoint {
184 remote-endpoint = <&xb 184 remote-endpoint = <&xbar_i2s1_ep>;
185 }; 185 };
186 }; 186 };
187 187
188 i2s1_port: port@1 { 188 i2s1_port: port@1 {
189 reg = <0x1>; 189 reg = <0x1>;
190 190
191 i2s1_dap: endpoint { 191 i2s1_dap: endpoint {
192 dai-format = "i2s"; 192 dai-format = "i2s";
193 }; 193 };
194 }; 194 };
195 }; 195 };
196 }; 196 };
197 }; 197 };
198 198
199 ... 199 ...
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