1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/nvidi 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-ac97.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NVIDIA Tegra20 AC97 controller 7 title: NVIDIA Tegra20 AC97 controller
8 8
9 maintainers: 9 maintainers:
10 - Thierry Reding <treding@nvidia.com> 10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com> 11 - Jon Hunter <jonathanh@nvidia.com>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 const: nvidia,tegra20-ac97 15 const: nvidia,tegra20-ac97
16 16
17 reg: 17 reg:
18 maxItems: 1 18 maxItems: 1
19 19
20 resets: 20 resets:
21 maxItems: 1 21 maxItems: 1
22 22
23 reset-names: 23 reset-names:
24 const: ac97 24 const: ac97
25 25
26 interrupts: 26 interrupts:
27 maxItems: 1 27 maxItems: 1
28 28
29 clocks: 29 clocks:
30 maxItems: 1 30 maxItems: 1
31 31
32 dmas: 32 dmas:
33 maxItems: 2 33 maxItems: 2
34 34
35 dma-names: 35 dma-names:
36 items: 36 items:
37 - const: rx 37 - const: rx
38 - const: tx 38 - const: tx
39 39
40 nvidia,codec-reset-gpios: 40 nvidia,codec-reset-gpios:
41 description: Reset pin of external AC97 co 41 description: Reset pin of external AC97 codec
42 maxItems: 1 42 maxItems: 1
43 43
44 nvidia,codec-sync-gpios: 44 nvidia,codec-sync-gpios:
45 description: AC97 DAP _FS line 45 description: AC97 DAP _FS line
46 maxItems: 1 46 maxItems: 1
47 47
48 required: 48 required:
49 - compatible 49 - compatible
50 - reg 50 - reg
51 - resets 51 - resets
52 - reset-names 52 - reset-names
53 - interrupts 53 - interrupts
54 - clocks 54 - clocks
55 - dmas 55 - dmas
56 - dma-names 56 - dma-names
57 - nvidia,codec-reset-gpios 57 - nvidia,codec-reset-gpios
58 - nvidia,codec-sync-gpios 58 - nvidia,codec-sync-gpios
59 59
60 additionalProperties: false 60 additionalProperties: false
61 61
62 examples: 62 examples:
63 - | 63 - |
64 #include <dt-bindings/clock/tegra20-car.h> 64 #include <dt-bindings/clock/tegra20-car.h>
65 #include <dt-bindings/gpio/tegra-gpio.h> 65 #include <dt-bindings/gpio/tegra-gpio.h>
66 #include <dt-bindings/interrupt-controller 66 #include <dt-bindings/interrupt-controller/arm-gic.h>
67 #include <dt-bindings/interrupt-controller 67 #include <dt-bindings/interrupt-controller/irq.h>
68 #include <dt-bindings/gpio/gpio.h> 68 #include <dt-bindings/gpio/gpio.h>
69 69
70 ac97@70002000 { 70 ac97@70002000 {
71 compatible = "nvidia,tegra20-ac97"; 71 compatible = "nvidia,tegra20-ac97";
72 reg = <0x70002000 0x200>; 72 reg = <0x70002000 0x200>;
73 resets = <&tegra_car 3>; 73 resets = <&tegra_car 3>;
74 reset-names = "ac97"; 74 reset-names = "ac97";
75 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVE 75 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
76 clocks = <&tegra_car 3>; 76 clocks = <&tegra_car 3>;
77 dmas = <&apbdma 12>, <&apbdma 12>; 77 dmas = <&apbdma 12>, <&apbdma 12>;
78 dma-names = "rx", "tx"; 78 dma-names = "rx", "tx";
79 nvidia,codec-reset-gpios = <&gpio TEGR 79 nvidia,codec-reset-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
80 nvidia,codec-sync-gpios = <&gpio TEGRA 80 nvidia,codec-sync-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
81 }; 81 };
82 ... 82 ...
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