1 RT5682 audio CODEC 1 RT5682 audio CODEC
2 2
3 This device supports I2C only. 3 This device supports I2C only.
4 4
5 Required properties: 5 Required properties:
6 6
7 - compatible : "realtek,rt5682" or "realtek,rt 7 - compatible : "realtek,rt5682" or "realtek,rt5682i"
8 8
9 - reg : The I2C address of the device. 9 - reg : The I2C address of the device.
10 10
11 - AVDD-supply: phandle to the regulator supply <<
12 AVDD pin <<
13 <<
14 - MICVDD-supply: phandle to the regulator supp <<
15 bias through the MICVDD pin. Either MICVDD o <<
16 <<
17 - VBAT-supply: phandle to the regulator supply <<
18 VBAT pin. Either MICVDD or VBAT should be pr <<
19 <<
20 - DBVDD-supply: phandle to the regulator suppl <<
21 pin. <<
22 <<
23 - LDO1-IN-supply: phandle to the regulator sup <<
24 and charge pump through the LDO1_IN pin. <<
25 <<
26 Optional properties: 11 Optional properties:
27 12
28 - interrupts : The CODEC's interrupt output. 13 - interrupts : The CODEC's interrupt output.
29 14
30 - realtek,dmic1-data-pin 15 - realtek,dmic1-data-pin
31 0: dmic1 is not used 16 0: dmic1 is not used
32 1: using GPIO2 pin as dmic1 data pin 17 1: using GPIO2 pin as dmic1 data pin
33 2: using GPIO5 pin as dmic1 data pin 18 2: using GPIO5 pin as dmic1 data pin
34 19
35 - realtek,dmic1-clk-pin 20 - realtek,dmic1-clk-pin
36 0: using GPIO1 pin as dmic1 clock pin 21 0: using GPIO1 pin as dmic1 clock pin
37 1: using GPIO3 pin as dmic1 clock pin 22 1: using GPIO3 pin as dmic1 clock pin
38 23
39 - realtek,jd-src 24 - realtek,jd-src
40 0: No JD is used 25 0: No JD is used
41 1: using JD1 as JD source 26 1: using JD1 as JD source
42 27
43 - realtek,ldo1-en-gpios : The GPIO that contro 28 - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
44 29
45 - realtek,btndet-delay 30 - realtek,btndet-delay
46 The debounce delay for push button. 31 The debounce delay for push button.
47 The delay time is realtek,btndet-delay value 32 The delay time is realtek,btndet-delay value multiple of 8.192 ms.
48 If absent, the default is 16. 33 If absent, the default is 16.
49 34
50 - #clock-cells : Should be set to '<1>', wclk 35 - #clock-cells : Should be set to '<1>', wclk and bclk sources provided.
51 - clock-output-names : Name given for DAI cloc 36 - clock-output-names : Name given for DAI clocks output.
52 37
53 - clocks : phandle and clock specifier for cod 38 - clocks : phandle and clock specifier for codec MCLK.
54 - clock-names : Clock name string for 'clocks' 39 - clock-names : Clock name string for 'clocks' attribute, should be "mclk".
55 40
56 - realtek,dmic-clk-rate-hz : Set the clock rat 41 - realtek,dmic-clk-rate-hz : Set the clock rate (hz) for the requirement of
57 the particular DMIC. 42 the particular DMIC.
58 43
59 - realtek,dmic-delay-ms : Set the delay time ( 44 - realtek,dmic-delay-ms : Set the delay time (ms) for the requirement of
60 the particular DMIC. 45 the particular DMIC.
61 46
62 - realtek,dmic-clk-driving-high : Set the high !! 47 - realtek,dmic-clk-driving-high : Set the high drving of the DMIC clock out.
63 <<
64 - #sound-dai-cells: Should be set to '<1>'. <<
65 48
66 Pins on the device (for linking into audio rou 49 Pins on the device (for linking into audio routes) for RT5682:
67 50
68 * DMIC L1 51 * DMIC L1
69 * DMIC R1 52 * DMIC R1
70 * IN1P 53 * IN1P
71 * HPOL 54 * HPOL
72 * HPOR 55 * HPOR
73 56
74 Example: 57 Example:
75 58
76 rt5682 { 59 rt5682 {
77 compatible = "realtek,rt5682i"; 60 compatible = "realtek,rt5682i";
78 reg = <0x1a>; 61 reg = <0x1a>;
79 interrupt-parent = <&gpio>; 62 interrupt-parent = <&gpio>;
80 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYP 63 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>;
81 realtek,ldo1-en-gpios = 64 realtek,ldo1-en-gpios =
82 <&gpio TEGRA_GPIO(R, 2) GPIO_A 65 <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
83 realtek,dmic1-data-pin = <1>; 66 realtek,dmic1-data-pin = <1>;
84 realtek,dmic1-clk-pin = <1>; 67 realtek,dmic1-clk-pin = <1>;
85 realtek,jd-src = <1>; 68 realtek,jd-src = <1>;
86 realtek,btndet-delay = <16>; 69 realtek,btndet-delay = <16>;
87 70
88 #clock-cells = <1>; 71 #clock-cells = <1>;
89 clock-output-names = "rt5682-dai-wclk" 72 clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk";
90 73
91 clocks = <&osc>; 74 clocks = <&osc>;
92 clock-names = "mclk"; 75 clock-names = "mclk";
93 <<
94 AVDD-supply = <&avdd_reg>; <<
95 MICVDD-supply = <&micvdd_reg>; <<
96 DBVDD-supply = <&dbvdd_reg>; <<
97 LDO1-IN-supply = <&ldo1_in_reg>; <<
98 }; 76 };
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