1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/samsu 4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Samsung SoC I2S controller 7 title: Samsung SoC I2S controller
8 8
9 maintainers: 9 maintainers:
10 - Krzysztof Kozlowski <krzk@kernel.org> 10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com> 11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 12
13 allOf: 13 allOf:
14 - $ref: dai-common.yaml# 14 - $ref: dai-common.yaml#
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 description: | 18 description: |
19 samsung,s3c6410-i2s: for 8/16/24bit ster 19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
20 20
21 samsung,s5pv210-i2s: for 8/16/24bit mult 21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
22 secondary FIFO, s/w reset control and in 22 secondary FIFO, s/w reset control and internal mux for root clock
23 source. 23 source.
24 24
25 samsung,exynos5420-i2s: for 8/16/24bit m 25 samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for
26 playback, stereo channel capture, second 26 playback, stereo channel capture, secondary FIFO using internal
27 or external DMA, s/w reset control, inte 27 or external DMA, s/w reset control, internal mux for root clock
28 source and 7.1 channel TDM support for p 28 source and 7.1 channel TDM support for playback; TDM (Time division
29 multiplexing) is to allow transfer of mu 29 multiplexing) is to allow transfer of multiple channel audio data on
30 single data line. 30 single data line.
31 31
32 samsung,exynos7-i2s: with all the availa 32 samsung,exynos7-i2s: with all the available features of Exynos5 I2S.
33 Exynos7 I2S has 7.1 channel TDM support 33 Exynos7 I2S has 7.1 channel TDM support for capture, secondary FIFO
34 with only external DMA and more number o 34 with only external DMA and more number of root clock sampling
35 frequencies. 35 frequencies.
36 36
37 samsung,exynos7-i2s1: I2S1 on previous s 37 samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports
38 stereo channels. Exynos7 I2S1 upgraded t 38 stereo channels. Exynos7 I2S1 upgraded to 5.1 multichannel with
39 slightly modified bit offsets. 39 slightly modified bit offsets.
40 40
41 tesla,fsd-i2s: for 8/16/24bit stereo cha 41 tesla,fsd-i2s: for 8/16/24bit stereo channel I2S for playback and
42 capture, secondary FIFO using external D 42 capture, secondary FIFO using external DMA, s/w reset control,
43 internal mux for root clock source with 43 internal mux for root clock source with all root clock sampling
44 frequencies supported by Exynos7 I2S and 44 frequencies supported by Exynos7 I2S and 7.1 channel TDM support
45 for playback and capture TDM (Time divis 45 for playback and capture TDM (Time division multiplexing) to allow
46 transfer of multiple channel audio data 46 transfer of multiple channel audio data on single data line.
47 oneOf: 47 oneOf:
48 - enum: 48 - enum:
49 - samsung,s3c6410-i2s 49 - samsung,s3c6410-i2s
50 - samsung,s5pv210-i2s 50 - samsung,s5pv210-i2s
51 - samsung,exynos5420-i2s 51 - samsung,exynos5420-i2s
52 - samsung,exynos7-i2s 52 - samsung,exynos7-i2s
53 - samsung,exynos7-i2s1 53 - samsung,exynos7-i2s1
54 - tesla,fsd-i2s 54 - tesla,fsd-i2s
55 - items: 55 - items:
56 - enum: 56 - enum:
57 - samsung,exynos5433-i2s 57 - samsung,exynos5433-i2s
58 - const: samsung,exynos7-i2s 58 - const: samsung,exynos7-i2s
59 59
60 '#address-cells': 60 '#address-cells':
61 const: 1 61 const: 1
62 62
63 '#size-cells': 63 '#size-cells':
64 const: 0 64 const: 0
65 65
66 reg: 66 reg:
67 maxItems: 1 67 maxItems: 1
68 68
69 dmas: 69 dmas:
70 minItems: 2 70 minItems: 2
71 maxItems: 3 71 maxItems: 3
72 72
73 dma-names: 73 dma-names:
74 oneOf: 74 oneOf:
75 - items: 75 - items:
76 - const: tx 76 - const: tx
77 - const: rx 77 - const: rx
78 - items: 78 - items:
79 - const: tx 79 - const: tx
80 - const: rx 80 - const: rx
81 - const: tx-sec 81 - const: tx-sec
82 82
83 clocks: 83 clocks:
84 minItems: 1 84 minItems: 1
85 maxItems: 3 85 maxItems: 3
86 86
87 clock-names: 87 clock-names:
88 oneOf: 88 oneOf:
89 - items: 89 - items:
90 - const: iis 90 - const: iis
91 - items: # for I2S0 91 - items: # for I2S0
92 - const: iis 92 - const: iis
93 - const: i2s_opclk0 93 - const: i2s_opclk0
94 - const: i2s_opclk1 94 - const: i2s_opclk1
95 - items: # for I2S1 and I2S2 95 - items: # for I2S1 and I2S2
96 - const: iis 96 - const: iis
97 - const: i2s_opclk0 97 - const: i2s_opclk0
98 description: | 98 description: |
99 "iis" is the I2S bus clock and i2s_opclk 99 "iis" is the I2S bus clock and i2s_opclk0, i2s_opclk1 are sources
100 of the root clock. I2S0 has internal mux 100 of the root clock. I2S0 has internal mux to select the source
101 of root clock and I2S1 and I2S2 doesn't 101 of root clock and I2S1 and I2S2 doesn't have any such mux.
102 102
103 "#clock-cells": 103 "#clock-cells":
104 const: 1 104 const: 1
105 105
106 clock-output-names: 106 clock-output-names:
107 deprecated: true 107 deprecated: true
108 oneOf: 108 oneOf:
109 - items: # for I2S0 109 - items: # for I2S0
110 - const: i2s_cdclk0 110 - const: i2s_cdclk0
111 - items: # for I2S1 111 - items: # for I2S1
112 - const: i2s_cdclk1 112 - const: i2s_cdclk1
113 - items: # for I2S2 113 - items: # for I2S2
114 - const: i2s_cdclk2 114 - const: i2s_cdclk2
115 description: Names of the CDCLK I2S output 115 description: Names of the CDCLK I2S output clocks.
116 116
117 interrupts: 117 interrupts:
118 maxItems: 1 118 maxItems: 1
119 119
120 samsung,idma-addr: 120 samsung,idma-addr:
121 $ref: /schemas/types.yaml#/definitions/uin 121 $ref: /schemas/types.yaml#/definitions/uint32
122 description: | 122 description: |
123 Internal DMA register base address of th 123 Internal DMA register base address of the audio
124 subsystem (used in secondary sound sourc 124 subsystem (used in secondary sound source).
125 125
126 power-domains: 126 power-domains:
127 maxItems: 1 127 maxItems: 1
128 128
129 "#sound-dai-cells": 129 "#sound-dai-cells":
130 const: 1 130 const: 1
131 131
132 required: 132 required:
133 - compatible 133 - compatible
134 - reg 134 - reg
135 - dmas 135 - dmas
136 - dma-names 136 - dma-names
137 - clocks 137 - clocks
138 - clock-names 138 - clock-names
139 139
140 unevaluatedProperties: false 140 unevaluatedProperties: false
141 141
142 examples: 142 examples:
143 - | 143 - |
144 #include <dt-bindings/clock/exynos-audss-c 144 #include <dt-bindings/clock/exynos-audss-clk.h>
145 145
146 i2s0: i2s@3830000 { 146 i2s0: i2s@3830000 {
147 compatible = "samsung,s5pv210-i2s"; 147 compatible = "samsung,s5pv210-i2s";
148 reg = <0x03830000 0x100>; 148 reg = <0x03830000 0x100>;
149 dmas = <&pdma0 10>, 149 dmas = <&pdma0 10>,
150 <&pdma0 9>, 150 <&pdma0 9>,
151 <&pdma0 8>; 151 <&pdma0 8>;
152 dma-names = "tx", "rx", "tx-sec"; 152 dma-names = "tx", "rx", "tx-sec";
153 clocks = <&clock_audss EXYNOS_I2S_BUS> 153 clocks = <&clock_audss EXYNOS_I2S_BUS>,
154 <&clock_audss EXYNOS_I2S_BUS>, 154 <&clock_audss EXYNOS_I2S_BUS>,
155 <&clock_audss EXYNOS_SCLK_I2S> 155 <&clock_audss EXYNOS_SCLK_I2S>;
156 clock-names = "iis", "i2s_opclk0", "i2 156 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
157 #clock-cells = <1>; 157 #clock-cells = <1>;
158 samsung,idma-addr = <0x03000000>; 158 samsung,idma-addr = <0x03000000>;
159 pinctrl-names = "default"; 159 pinctrl-names = "default";
160 pinctrl-0 = <&i2s0_bus>; 160 pinctrl-0 = <&i2s0_bus>;
161 #sound-dai-cells = <1>; 161 #sound-dai-cells = <1>;
162 }; 162 };
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