1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/sound/ti,tl
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Texas Instruments TLV320ADC3001/TLV320A
8
9 maintainers:
10 - Ricard Wanderlof <ricardw@axis.com>
11
12 description: |
13 Texas Instruments TLV320ADC3001 and TLV320AD
14 https://www.ti.com/product/TLV320ADC3001
15 https://www.ti.com/product/TLV320ADC3101
16
17 allOf:
18 - $ref: dai-common.yaml#
19
20 properties:
21 compatible:
22 enum:
23 - ti,tlv320adc3001
24 - ti,tlv320adc3101
25
26 reg:
27 maxItems: 1
28 description: I2C address
29
30 '#sound-dai-cells':
31 const: 0
32
33 '#gpio-cells':
34 const: 2
35
36 gpio-controller: true
37
38 reset-gpios:
39 maxItems: 1
40 description: GPIO pin used for codec reset
41
42 clocks:
43 maxItems: 1
44 description: Master clock (MCLK)
45
46 ti,dmdin-gpio1:
47 $ref: /schemas/types.yaml#/definitions/uin
48 enum:
49 - 0 # ADC3XXX_GPIO_DISABLED - I/O
50 - 1 # ADC3XXX_GPIO_INPUT - Vari
51 - 2 # ADC3XXX_GPIO_GPI - Gene
52 - 3 # ADC3XXX_GPIO_GPO - Gene
53 - 4 # ADC3XXX_GPIO_CLKOUT - Cloc
54 - 5 # ADC3XXX_GPIO_INT1 - INT1
55 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Code
56 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Code
57 default: 0
58 description: |
59 Configuration for DMDIN/GPIO1 pin.
60
61 When ADC3XXX_GPIO_GPO is selected, the p
62 GPIO framework, as pin number 0 on the d
63
64 ti,dmclk-gpio2:
65 $ref: /schemas/types.yaml#/definitions/uin
66 enum:
67 - 0 # ADC3XXX_GPIO_DISABLED - I/O
68 - 1 # ADC3XXX_GPIO_INPUT - Vari
69 - 2 # ADC3XXX_GPIO_GPI - Gene
70 - 3 # ADC3XXX_GPIO_GPO - Gene
71 - 4 # ADC3XXX_GPIO_CLKOUT - Cloc
72 - 5 # ADC3XXX_GPIO_INT1 - INT1
73 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Code
74 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Code
75 default: 0
76 description: |
77 Configuration for DMCLK/GPIO2 pin.
78
79 When ADC3XXX_GPIO_GPO is selected, the p
80 GPIO framework, as pin number 1 on the d
81
82 Note that there is currently no support
83 inputs.
84
85 ti,micbias1-gpo:
86 type: boolean
87 description: |
88 When set, the MICBIAS1 pin may be contro
89 as pin number 3 on the device.
90
91 In this mode, when the pin is activated,
92 specified by the ti,micbias1-vg property
93 float.
94
95 ti,micbias2-gpo:
96 type: boolean
97 description: |
98 When set, the MICBIAS2 pin may be contro
99 as pin number 4 on the device.
100
101 In this mode, when the pin is activated,
102 specified by the ti,micbias2-vg property
103 float.
104
105 ti,micbias1-vg:
106 $ref: /schemas/types.yaml#/definitions/uin
107 enum:
108 - 0 # ADC3XXX_MICBIAS_OFF - Mic
109 - 1 # ADC3XXX_MICBIAS_2_0V - Mic
110 - 2 # ADC3XXX_MICBIAS_2_5V - Mic
111 - 3 # ADC3XXX_MICBIAS_AVDD - Mic
112 default: 0
113 description: |
114 Mic bias voltage output on MICBIAS1 pin
115
116 ti,micbias2-vg:
117 $ref: /schemas/types.yaml#/definitions/uin
118 enum:
119 - 0 # ADC3XXX_MICBIAS_OFF - Mic
120 - 1 # ADC3XXX_MICBIAS_2_0V - Mic
121 - 2 # ADC3XXX_MICBIAS_2_5V - Mic
122 - 3 # ADC3XXX_MICBIAS_AVDD - Mic
123 default: 0
124 description: |
125 Mic bias voltage output on MICBIAS2 pin
126
127 dependencies:
128 ti,micbias1-gpo: ['ti,micbias1-vg']
129 ti,micbias2-gpo: ['ti,micbias2-vg']
130
131 required:
132 - compatible
133 - reg
134 - clocks
135
136 unevaluatedProperties: false
137
138 examples:
139 - |
140
141 #include <dt-bindings/gpio/gpio.h>
142 #include <dt-bindings/sound/tlv320adc3xxx.
143
144 i2c {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 tlv320adc3101: audio-codec@18 {
148 compatible = "ti,tlv320adc3101";
149 reg = <0x18>;
150 reset-gpios = <&gpio_pc 3 GPIO_ACT
151 clocks = <&audio_mclk>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 ti,dmdin-gpio1 = <ADC3XXX_GPIO_GPO
155 ti,micbias1-vg = <ADC3XXX_MICBIAS_
156 };
157 };
158
159 audio_mclk: clock {
160 compatible = "fixed-clock";
161 #clock-cells = <0>;
162 clock-frequency = <24576000>;
163 };
164 ...
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