1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/ti,tl 4 $id: http://devicetree.org/schemas/sound/ti,tlv320adc3xxx.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Texas Instruments TLV320ADC3001/TLV320A 7 title: Texas Instruments TLV320ADC3001/TLV320ADC3101 Stereo ADC
8 8
9 maintainers: 9 maintainers:
10 - Ricard Wanderlof <ricardw@axis.com> 10 - Ricard Wanderlof <ricardw@axis.com>
11 11
12 description: | 12 description: |
13 Texas Instruments TLV320ADC3001 and TLV320AD 13 Texas Instruments TLV320ADC3001 and TLV320ADC3101 Stereo ADC
14 https://www.ti.com/product/TLV320ADC3001 14 https://www.ti.com/product/TLV320ADC3001
15 https://www.ti.com/product/TLV320ADC3101 15 https://www.ti.com/product/TLV320ADC3101
16 16
17 allOf: <<
18 - $ref: dai-common.yaml# <<
19 <<
20 properties: 17 properties:
21 compatible: 18 compatible:
22 enum: 19 enum:
23 - ti,tlv320adc3001 20 - ti,tlv320adc3001
24 - ti,tlv320adc3101 21 - ti,tlv320adc3101
25 22
26 reg: 23 reg:
27 maxItems: 1 24 maxItems: 1
28 description: I2C address 25 description: I2C address
29 26
30 '#sound-dai-cells': 27 '#sound-dai-cells':
31 const: 0 28 const: 0
32 29
33 '#gpio-cells': 30 '#gpio-cells':
34 const: 2 31 const: 2
35 32
36 gpio-controller: true 33 gpio-controller: true
37 34
38 reset-gpios: 35 reset-gpios:
39 maxItems: 1 36 maxItems: 1
40 description: GPIO pin used for codec reset 37 description: GPIO pin used for codec reset (RESET pin)
41 38
42 clocks: 39 clocks:
43 maxItems: 1 40 maxItems: 1
44 description: Master clock (MCLK) 41 description: Master clock (MCLK)
45 42
46 ti,dmdin-gpio1: 43 ti,dmdin-gpio1:
47 $ref: /schemas/types.yaml#/definitions/uin 44 $ref: /schemas/types.yaml#/definitions/uint32
48 enum: 45 enum:
49 - 0 # ADC3XXX_GPIO_DISABLED - I/O 46 - 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used
50 - 1 # ADC3XXX_GPIO_INPUT - Vari 47 - 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions
51 - 2 # ADC3XXX_GPIO_GPI - Gene 48 - 2 # ADC3XXX_GPIO_GPI - General purpose input
52 - 3 # ADC3XXX_GPIO_GPO - Gene 49 - 3 # ADC3XXX_GPIO_GPO - General purpose output
53 - 4 # ADC3XXX_GPIO_CLKOUT - Cloc 50 - 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg
54 - 5 # ADC3XXX_GPIO_INT1 - INT1 51 - 5 # ADC3XXX_GPIO_INT1 - INT1 output
55 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Code 52 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK
56 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Code 53 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
57 default: 0 54 default: 0
58 description: | 55 description: |
59 Configuration for DMDIN/GPIO1 pin. 56 Configuration for DMDIN/GPIO1 pin.
60 57
61 When ADC3XXX_GPIO_GPO is selected, the p !! 58 When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
62 GPIO framework, as pin number 0 on the d !! 59 ALSA control "GPIOx Output" to appear, as a switch control.
63 60
64 ti,dmclk-gpio2: 61 ti,dmclk-gpio2:
65 $ref: /schemas/types.yaml#/definitions/uin 62 $ref: /schemas/types.yaml#/definitions/uint32
66 enum: 63 enum:
67 - 0 # ADC3XXX_GPIO_DISABLED - I/O 64 - 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used
68 - 1 # ADC3XXX_GPIO_INPUT - Vari 65 - 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions
69 - 2 # ADC3XXX_GPIO_GPI - Gene 66 - 2 # ADC3XXX_GPIO_GPI - General purpose input
70 - 3 # ADC3XXX_GPIO_GPO - Gene 67 - 3 # ADC3XXX_GPIO_GPO - General purpose output
71 - 4 # ADC3XXX_GPIO_CLKOUT - Cloc 68 - 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg
72 - 5 # ADC3XXX_GPIO_INT1 - INT1 69 - 5 # ADC3XXX_GPIO_INT1 - INT1 output
73 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Code 70 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK
74 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Code 71 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
75 default: 0 72 default: 0
76 description: | 73 description: |
77 Configuration for DMCLK/GPIO2 pin. 74 Configuration for DMCLK/GPIO2 pin.
78 75
79 When ADC3XXX_GPIO_GPO is selected, the p !! 76 When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
80 GPIO framework, as pin number 1 on the d !! 77 ALSA control "GPIOx Output" to appear, as a switch control.
81 78
82 Note that there is currently no support 79 Note that there is currently no support for reading the GPIO pins as
83 inputs. 80 inputs.
84 81
85 ti,micbias1-gpo: <<
86 type: boolean <<
87 description: | <<
88 When set, the MICBIAS1 pin may be contro <<
89 as pin number 3 on the device. <<
90 <<
91 In this mode, when the pin is activated, <<
92 specified by the ti,micbias1-vg property <<
93 float. <<
94 <<
95 ti,micbias2-gpo: <<
96 type: boolean <<
97 description: | <<
98 When set, the MICBIAS2 pin may be contro <<
99 as pin number 4 on the device. <<
100 <<
101 In this mode, when the pin is activated, <<
102 specified by the ti,micbias2-vg property <<
103 float. <<
104 <<
105 ti,micbias1-vg: 82 ti,micbias1-vg:
106 $ref: /schemas/types.yaml#/definitions/uin 83 $ref: /schemas/types.yaml#/definitions/uint32
107 enum: 84 enum:
108 - 0 # ADC3XXX_MICBIAS_OFF - Mic 85 - 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down
109 - 1 # ADC3XXX_MICBIAS_2_0V - Mic 86 - 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V
110 - 2 # ADC3XXX_MICBIAS_2_5V - Mic 87 - 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V
111 - 3 # ADC3XXX_MICBIAS_AVDD - Mic 88 - 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply
112 default: 0 89 default: 0
113 description: | 90 description: |
114 Mic bias voltage output on MICBIAS1 pin 91 Mic bias voltage output on MICBIAS1 pin
115 92
116 ti,micbias2-vg: 93 ti,micbias2-vg:
117 $ref: /schemas/types.yaml#/definitions/uin 94 $ref: /schemas/types.yaml#/definitions/uint32
118 enum: 95 enum:
119 - 0 # ADC3XXX_MICBIAS_OFF - Mic 96 - 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down
120 - 1 # ADC3XXX_MICBIAS_2_0V - Mic 97 - 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V
121 - 2 # ADC3XXX_MICBIAS_2_5V - Mic 98 - 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V
122 - 3 # ADC3XXX_MICBIAS_AVDD - Mic 99 - 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply
123 default: 0 100 default: 0
124 description: | 101 description: |
125 Mic bias voltage output on MICBIAS2 pin 102 Mic bias voltage output on MICBIAS2 pin
126 103
127 dependencies: <<
128 ti,micbias1-gpo: ['ti,micbias1-vg'] <<
129 ti,micbias2-gpo: ['ti,micbias2-vg'] <<
130 <<
131 required: 104 required:
132 - compatible 105 - compatible
133 - reg 106 - reg
134 - clocks 107 - clocks
135 108
136 unevaluatedProperties: false !! 109 additionalProperties: false
137 110
138 examples: 111 examples:
139 - | 112 - |
140 113
141 #include <dt-bindings/gpio/gpio.h> 114 #include <dt-bindings/gpio/gpio.h>
142 #include <dt-bindings/sound/tlv320adc3xxx. 115 #include <dt-bindings/sound/tlv320adc3xxx.h>
143 116
144 i2c { 117 i2c {
145 #address-cells = <1>; 118 #address-cells = <1>;
146 #size-cells = <0>; 119 #size-cells = <0>;
147 tlv320adc3101: audio-codec@18 { 120 tlv320adc3101: audio-codec@18 {
148 compatible = "ti,tlv320adc3101"; 121 compatible = "ti,tlv320adc3101";
149 reg = <0x18>; 122 reg = <0x18>;
150 reset-gpios = <&gpio_pc 3 GPIO_ACT 123 reset-gpios = <&gpio_pc 3 GPIO_ACTIVE_LOW>;
151 clocks = <&audio_mclk>; 124 clocks = <&audio_mclk>;
152 gpio-controller; 125 gpio-controller;
153 #gpio-cells = <2>; 126 #gpio-cells = <2>;
154 ti,dmdin-gpio1 = <ADC3XXX_GPIO_GPO 127 ti,dmdin-gpio1 = <ADC3XXX_GPIO_GPO>;
155 ti,micbias1-vg = <ADC3XXX_MICBIAS_ 128 ti,micbias1-vg = <ADC3XXX_MICBIAS_AVDD>;
156 }; 129 };
157 }; 130 };
158 131
159 audio_mclk: clock { 132 audio_mclk: clock {
160 compatible = "fixed-clock"; 133 compatible = "fixed-clock";
161 #clock-cells = <0>; 134 #clock-cells = <0>;
162 clock-frequency = <24576000>; 135 clock-frequency = <24576000>;
163 }; 136 };
164 ... 137 ...
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