1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/sound/ti,tl 4 $id: http://devicetree.org/schemas/sound/ti,tlv320adc3xxx.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Texas Instruments TLV320ADC3001/TLV320A 7 title: Texas Instruments TLV320ADC3001/TLV320ADC3101 Stereo ADC
8 8
9 maintainers: 9 maintainers:
10 - Ricard Wanderlof <ricardw@axis.com> 10 - Ricard Wanderlof <ricardw@axis.com>
11 11
12 description: | 12 description: |
13 Texas Instruments TLV320ADC3001 and TLV320AD 13 Texas Instruments TLV320ADC3001 and TLV320ADC3101 Stereo ADC
14 https://www.ti.com/product/TLV320ADC3001 14 https://www.ti.com/product/TLV320ADC3001
15 https://www.ti.com/product/TLV320ADC3101 15 https://www.ti.com/product/TLV320ADC3101
16 16
17 allOf: 17 allOf:
18 - $ref: dai-common.yaml# 18 - $ref: dai-common.yaml#
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 enum: 22 enum:
23 - ti,tlv320adc3001 23 - ti,tlv320adc3001
24 - ti,tlv320adc3101 24 - ti,tlv320adc3101
25 25
26 reg: 26 reg:
27 maxItems: 1 27 maxItems: 1
28 description: I2C address 28 description: I2C address
29 29
30 '#sound-dai-cells': 30 '#sound-dai-cells':
31 const: 0 31 const: 0
32 32
33 '#gpio-cells': 33 '#gpio-cells':
34 const: 2 34 const: 2
35 35
36 gpio-controller: true 36 gpio-controller: true
37 37
38 reset-gpios: 38 reset-gpios:
39 maxItems: 1 39 maxItems: 1
40 description: GPIO pin used for codec reset 40 description: GPIO pin used for codec reset (RESET pin)
41 41
42 clocks: 42 clocks:
43 maxItems: 1 43 maxItems: 1
44 description: Master clock (MCLK) 44 description: Master clock (MCLK)
45 45
46 ti,dmdin-gpio1: 46 ti,dmdin-gpio1:
47 $ref: /schemas/types.yaml#/definitions/uin 47 $ref: /schemas/types.yaml#/definitions/uint32
48 enum: 48 enum:
49 - 0 # ADC3XXX_GPIO_DISABLED - I/O 49 - 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used
50 - 1 # ADC3XXX_GPIO_INPUT - Vari 50 - 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions
51 - 2 # ADC3XXX_GPIO_GPI - Gene 51 - 2 # ADC3XXX_GPIO_GPI - General purpose input
52 - 3 # ADC3XXX_GPIO_GPO - Gene 52 - 3 # ADC3XXX_GPIO_GPO - General purpose output
53 - 4 # ADC3XXX_GPIO_CLKOUT - Cloc 53 - 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg
54 - 5 # ADC3XXX_GPIO_INT1 - INT1 54 - 5 # ADC3XXX_GPIO_INT1 - INT1 output
55 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Code 55 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK
56 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Code 56 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
57 default: 0 57 default: 0
58 description: | 58 description: |
59 Configuration for DMDIN/GPIO1 pin. 59 Configuration for DMDIN/GPIO1 pin.
60 60
61 When ADC3XXX_GPIO_GPO is selected, the p !! 61 When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
62 GPIO framework, as pin number 0 on the d !! 62 ALSA control "GPIOx Output" to appear, as a switch control.
63 63
64 ti,dmclk-gpio2: 64 ti,dmclk-gpio2:
65 $ref: /schemas/types.yaml#/definitions/uin 65 $ref: /schemas/types.yaml#/definitions/uint32
66 enum: 66 enum:
67 - 0 # ADC3XXX_GPIO_DISABLED - I/O 67 - 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used
68 - 1 # ADC3XXX_GPIO_INPUT - Vari 68 - 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions
69 - 2 # ADC3XXX_GPIO_GPI - Gene 69 - 2 # ADC3XXX_GPIO_GPI - General purpose input
70 - 3 # ADC3XXX_GPIO_GPO - Gene 70 - 3 # ADC3XXX_GPIO_GPO - General purpose output
71 - 4 # ADC3XXX_GPIO_CLKOUT - Cloc 71 - 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg
72 - 5 # ADC3XXX_GPIO_INT1 - INT1 72 - 5 # ADC3XXX_GPIO_INT1 - INT1 output
73 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Code 73 - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK
74 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Code 74 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
75 default: 0 75 default: 0
76 description: | 76 description: |
77 Configuration for DMCLK/GPIO2 pin. 77 Configuration for DMCLK/GPIO2 pin.
78 78
79 When ADC3XXX_GPIO_GPO is selected, the p !! 79 When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
80 GPIO framework, as pin number 1 on the d !! 80 ALSA control "GPIOx Output" to appear, as a switch control.
81 81
82 Note that there is currently no support 82 Note that there is currently no support for reading the GPIO pins as
83 inputs. 83 inputs.
84 84
85 ti,micbias1-gpo: <<
86 type: boolean <<
87 description: | <<
88 When set, the MICBIAS1 pin may be contro <<
89 as pin number 3 on the device. <<
90 <<
91 In this mode, when the pin is activated, <<
92 specified by the ti,micbias1-vg property <<
93 float. <<
94 <<
95 ti,micbias2-gpo: <<
96 type: boolean <<
97 description: | <<
98 When set, the MICBIAS2 pin may be contro <<
99 as pin number 4 on the device. <<
100 <<
101 In this mode, when the pin is activated, <<
102 specified by the ti,micbias2-vg property <<
103 float. <<
104 <<
105 ti,micbias1-vg: 85 ti,micbias1-vg:
106 $ref: /schemas/types.yaml#/definitions/uin 86 $ref: /schemas/types.yaml#/definitions/uint32
107 enum: 87 enum:
108 - 0 # ADC3XXX_MICBIAS_OFF - Mic 88 - 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down
109 - 1 # ADC3XXX_MICBIAS_2_0V - Mic 89 - 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V
110 - 2 # ADC3XXX_MICBIAS_2_5V - Mic 90 - 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V
111 - 3 # ADC3XXX_MICBIAS_AVDD - Mic 91 - 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply
112 default: 0 92 default: 0
113 description: | 93 description: |
114 Mic bias voltage output on MICBIAS1 pin 94 Mic bias voltage output on MICBIAS1 pin
115 95
116 ti,micbias2-vg: 96 ti,micbias2-vg:
117 $ref: /schemas/types.yaml#/definitions/uin 97 $ref: /schemas/types.yaml#/definitions/uint32
118 enum: 98 enum:
119 - 0 # ADC3XXX_MICBIAS_OFF - Mic 99 - 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down
120 - 1 # ADC3XXX_MICBIAS_2_0V - Mic 100 - 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V
121 - 2 # ADC3XXX_MICBIAS_2_5V - Mic 101 - 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V
122 - 3 # ADC3XXX_MICBIAS_AVDD - Mic 102 - 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply
123 default: 0 103 default: 0
124 description: | 104 description: |
125 Mic bias voltage output on MICBIAS2 pin 105 Mic bias voltage output on MICBIAS2 pin
126 <<
127 dependencies: <<
128 ti,micbias1-gpo: ['ti,micbias1-vg'] <<
129 ti,micbias2-gpo: ['ti,micbias2-vg'] <<
130 106
131 required: 107 required:
132 - compatible 108 - compatible
133 - reg 109 - reg
134 - clocks 110 - clocks
135 111
136 unevaluatedProperties: false 112 unevaluatedProperties: false
137 113
138 examples: 114 examples:
139 - | 115 - |
140 116
141 #include <dt-bindings/gpio/gpio.h> 117 #include <dt-bindings/gpio/gpio.h>
142 #include <dt-bindings/sound/tlv320adc3xxx. 118 #include <dt-bindings/sound/tlv320adc3xxx.h>
143 119
144 i2c { 120 i2c {
145 #address-cells = <1>; 121 #address-cells = <1>;
146 #size-cells = <0>; 122 #size-cells = <0>;
147 tlv320adc3101: audio-codec@18 { 123 tlv320adc3101: audio-codec@18 {
148 compatible = "ti,tlv320adc3101"; 124 compatible = "ti,tlv320adc3101";
149 reg = <0x18>; 125 reg = <0x18>;
150 reset-gpios = <&gpio_pc 3 GPIO_ACT 126 reset-gpios = <&gpio_pc 3 GPIO_ACTIVE_LOW>;
151 clocks = <&audio_mclk>; 127 clocks = <&audio_mclk>;
152 gpio-controller; 128 gpio-controller;
153 #gpio-cells = <2>; 129 #gpio-cells = <2>;
154 ti,dmdin-gpio1 = <ADC3XXX_GPIO_GPO 130 ti,dmdin-gpio1 = <ADC3XXX_GPIO_GPO>;
155 ti,micbias1-vg = <ADC3XXX_MICBIAS_ 131 ti,micbias1-vg = <ADC3XXX_MICBIAS_AVDD>;
156 }; 132 };
157 }; 133 };
158 134
159 audio_mclk: clock { 135 audio_mclk: clock {
160 compatible = "fixed-clock"; 136 compatible = "fixed-clock";
161 #clock-cells = <0>; 137 #clock-cells = <0>;
162 clock-frequency = <24576000>; 138 clock-frequency = <24576000>;
163 }; 139 };
164 ... 140 ...
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