1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022 Microchip Technology, Inc 2 # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/spi/atmel,a 5 $id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: Atmel SPI device 8 title: Atmel SPI device
9 9
10 maintainers: 10 maintainers:
11 - Tudor Ambarus <tudor.ambarus@linaro.org> !! 11 - Tudor Ambarus <tudor.ambarus@microchip.com>
12 12
13 allOf: 13 allOf:
14 - $ref: spi-controller.yaml# 14 - $ref: spi-controller.yaml#
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 oneOf: 18 oneOf:
19 - const: atmel,at91rm9200-spi 19 - const: atmel,at91rm9200-spi
20 - items: 20 - items:
21 - enum: !! 21 - const: microchip,sam9x60-spi
22 - microchip,sam9x60-spi <<
23 - microchip,sam9x7-spi <<
24 - microchip,sama7d65-spi <<
25 - const: atmel,at91rm9200-spi 22 - const: atmel,at91rm9200-spi
26 23
27 reg: 24 reg:
28 maxItems: 1 25 maxItems: 1
29 26
30 interrupts: 27 interrupts:
31 maxItems: 1 28 maxItems: 1
32 29
33 clock-names: 30 clock-names:
34 contains: 31 contains:
35 const: spi_clk 32 const: spi_clk
36 33
37 clocks: 34 clocks:
38 maxItems: 1 35 maxItems: 1
39 <<
40 dmas: <<
41 items: <<
42 - description: TX DMA Channel <<
43 - description: RX DMA Channel <<
44 <<
45 dma-names: <<
46 items: <<
47 - const: tx <<
48 - const: rx <<
49 36
50 atmel,fifo-size: 37 atmel,fifo-size:
51 $ref: /schemas/types.yaml#/definitions/uin 38 $ref: /schemas/types.yaml#/definitions/uint32
52 description: | 39 description: |
53 Maximum number of data the RX and TX FIF 40 Maximum number of data the RX and TX FIFOs can store for FIFO
54 capable SPI controllers. 41 capable SPI controllers.
55 enum: [ 16, 32 ] 42 enum: [ 16, 32 ]
56 43
57 required: 44 required:
58 - compatible 45 - compatible
59 - reg 46 - reg
60 - interrupts 47 - interrupts
61 - clock-names 48 - clock-names
62 - clocks 49 - clocks
63 50
64 unevaluatedProperties: false 51 unevaluatedProperties: false
65 52
66 examples: 53 examples:
67 - | 54 - |
68 #include <dt-bindings/gpio/gpio.h> 55 #include <dt-bindings/gpio/gpio.h>
69 #include <dt-bindings/interrupt-controller 56 #include <dt-bindings/interrupt-controller/irq.h>
70 57
71 spi1: spi@fffcc000 { 58 spi1: spi@fffcc000 {
72 compatible = "atmel,at91rm9200-spi"; 59 compatible = "atmel,at91rm9200-spi";
73 reg = <0xfffcc000 0x4000>; 60 reg = <0xfffcc000 0x4000>;
74 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5 61 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
75 #address-cells = <1>; 62 #address-cells = <1>;
76 #size-cells = <0>; 63 #size-cells = <0>;
77 clocks = <&spi1_clk>; 64 clocks = <&spi1_clk>;
78 clock-names = "spi_clk"; 65 clock-names = "spi_clk";
79 cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; 66 cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
80 atmel,fifo-size = <32>; 67 atmel,fifo-size = <32>;
81 68
82 mmc@0 { 69 mmc@0 {
83 compatible = "mmc-spi-slot"; 70 compatible = "mmc-spi-slot";
84 reg = <0>; 71 reg = <0>;
85 gpios = <&pioC 4 GPIO_ACTIVE_HIGH> 72 gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; /* CD */
86 spi-max-frequency = <25000000>; 73 spi-max-frequency = <25000000>;
87 }; 74 };
88 }; 75 };
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