1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2022 Microchip Technology, Inc 2 # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries 3 %YAML 1.2 3 %YAML 1.2 4 --- 4 --- 5 $id: http://devicetree.org/schemas/spi/atmel,a 5 $id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml# 6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 title: Atmel SPI device 8 title: Atmel SPI device 9 9 10 maintainers: 10 maintainers: 11 - Tudor Ambarus <tudor.ambarus@linaro.org> 11 - Tudor Ambarus <tudor.ambarus@linaro.org> 12 12 13 allOf: 13 allOf: 14 - $ref: spi-controller.yaml# 14 - $ref: spi-controller.yaml# 15 15 16 properties: 16 properties: 17 compatible: 17 compatible: 18 oneOf: 18 oneOf: 19 - const: atmel,at91rm9200-spi 19 - const: atmel,at91rm9200-spi 20 - items: 20 - items: 21 - enum: !! 21 - const: microchip,sam9x60-spi 22 - microchip,sam9x60-spi << 23 - microchip,sam9x7-spi << 24 - microchip,sama7d65-spi << 25 - const: atmel,at91rm9200-spi 22 - const: atmel,at91rm9200-spi 26 23 27 reg: 24 reg: 28 maxItems: 1 25 maxItems: 1 29 26 30 interrupts: 27 interrupts: 31 maxItems: 1 28 maxItems: 1 32 29 33 clock-names: 30 clock-names: 34 contains: 31 contains: 35 const: spi_clk 32 const: spi_clk 36 33 37 clocks: 34 clocks: 38 maxItems: 1 35 maxItems: 1 39 36 40 dmas: 37 dmas: 41 items: 38 items: 42 - description: TX DMA Channel 39 - description: TX DMA Channel 43 - description: RX DMA Channel 40 - description: RX DMA Channel 44 41 45 dma-names: 42 dma-names: 46 items: 43 items: 47 - const: tx 44 - const: tx 48 - const: rx 45 - const: rx 49 46 50 atmel,fifo-size: 47 atmel,fifo-size: 51 $ref: /schemas/types.yaml#/definitions/uin 48 $ref: /schemas/types.yaml#/definitions/uint32 52 description: | 49 description: | 53 Maximum number of data the RX and TX FIF 50 Maximum number of data the RX and TX FIFOs can store for FIFO 54 capable SPI controllers. 51 capable SPI controllers. 55 enum: [ 16, 32 ] 52 enum: [ 16, 32 ] 56 53 57 required: 54 required: 58 - compatible 55 - compatible 59 - reg 56 - reg 60 - interrupts 57 - interrupts 61 - clock-names 58 - clock-names 62 - clocks 59 - clocks 63 60 64 unevaluatedProperties: false 61 unevaluatedProperties: false 65 62 66 examples: 63 examples: 67 - | 64 - | 68 #include <dt-bindings/gpio/gpio.h> 65 #include <dt-bindings/gpio/gpio.h> 69 #include <dt-bindings/interrupt-controller 66 #include <dt-bindings/interrupt-controller/irq.h> 70 67 71 spi1: spi@fffcc000 { 68 spi1: spi@fffcc000 { 72 compatible = "atmel,at91rm9200-spi"; 69 compatible = "atmel,at91rm9200-spi"; 73 reg = <0xfffcc000 0x4000>; 70 reg = <0xfffcc000 0x4000>; 74 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5 71 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 75 #address-cells = <1>; 72 #address-cells = <1>; 76 #size-cells = <0>; 73 #size-cells = <0>; 77 clocks = <&spi1_clk>; 74 clocks = <&spi1_clk>; 78 clock-names = "spi_clk"; 75 clock-names = "spi_clk"; 79 cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; 76 cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; 80 atmel,fifo-size = <32>; 77 atmel,fifo-size = <32>; 81 78 82 mmc@0 { 79 mmc@0 { 83 compatible = "mmc-spi-slot"; 80 compatible = "mmc-spi-slot"; 84 reg = <0>; 81 reg = <0>; 85 gpios = <&pioC 4 GPIO_ACTIVE_HIGH> 82 gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; /* CD */ 86 spi-max-frequency = <25000000>; 83 spi-max-frequency = <25000000>; 87 }; 84 }; 88 }; 85 };
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