1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/spi/fsl-imx 4 $id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale (Enhanced) Configurable Seria 7 title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX
8 8
9 maintainers: 9 maintainers:
10 - Shawn Guo <shawnguo@kernel.org> 10 - Shawn Guo <shawnguo@kernel.org>
11 11
12 allOf: 12 allOf:
13 - $ref: /schemas/spi/spi-controller.yaml# 13 - $ref: /schemas/spi/spi-controller.yaml#
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 oneOf: 17 oneOf:
18 - const: fsl,imx1-cspi 18 - const: fsl,imx1-cspi
19 - const: fsl,imx21-cspi 19 - const: fsl,imx21-cspi
20 - const: fsl,imx27-cspi 20 - const: fsl,imx27-cspi
21 - const: fsl,imx31-cspi 21 - const: fsl,imx31-cspi
22 - const: fsl,imx35-cspi 22 - const: fsl,imx35-cspi
23 - const: fsl,imx51-ecspi 23 - const: fsl,imx51-ecspi
24 - const: fsl,imx53-ecspi 24 - const: fsl,imx53-ecspi
25 - items: 25 - items:
26 - enum: <<
27 - fsl,imx25-cspi <<
28 - fsl,imx50-cspi <<
29 - fsl,imx51-cspi <<
30 - fsl,imx53-cspi <<
31 - const: fsl,imx35-cspi <<
32 - items: <<
33 - const: fsl,imx8mp-ecspi 26 - const: fsl,imx8mp-ecspi
34 - const: fsl,imx6ul-ecspi 27 - const: fsl,imx6ul-ecspi
35 - items: 28 - items:
36 - enum: 29 - enum:
37 - fsl,imx50-ecspi 30 - fsl,imx50-ecspi
38 - fsl,imx6q-ecspi 31 - fsl,imx6q-ecspi
39 - fsl,imx6sx-ecspi 32 - fsl,imx6sx-ecspi
40 - fsl,imx6sl-ecspi 33 - fsl,imx6sl-ecspi
41 - fsl,imx6sll-ecspi 34 - fsl,imx6sll-ecspi
42 - fsl,imx6ul-ecspi 35 - fsl,imx6ul-ecspi
43 - fsl,imx7d-ecspi 36 - fsl,imx7d-ecspi
44 - fsl,imx8mq-ecspi 37 - fsl,imx8mq-ecspi
45 - fsl,imx8mm-ecspi 38 - fsl,imx8mm-ecspi
46 - fsl,imx8mn-ecspi 39 - fsl,imx8mn-ecspi
47 - const: fsl,imx51-ecspi 40 - const: fsl,imx51-ecspi
48 41
49 reg: 42 reg:
50 maxItems: 1 43 maxItems: 1
51 44
52 interrupts: 45 interrupts:
53 maxItems: 1 46 maxItems: 1
54 47
55 clocks: 48 clocks:
56 items: 49 items:
57 - description: SoC SPI ipg clock 50 - description: SoC SPI ipg clock
58 - description: SoC SPI per clock 51 - description: SoC SPI per clock
59 52
60 clock-names: 53 clock-names:
61 items: 54 items:
62 - const: ipg 55 - const: ipg
63 - const: per 56 - const: per
64 57
65 dmas: 58 dmas:
66 items: 59 items:
67 - description: DMA controller phandle an 60 - description: DMA controller phandle and request line for RX
68 - description: DMA controller phandle an 61 - description: DMA controller phandle and request line for TX
69 62
70 dma-names: 63 dma-names:
71 items: 64 items:
72 - const: rx 65 - const: rx
73 - const: tx 66 - const: tx
74 67
75 fsl,spi-rdy-drctl: 68 fsl,spi-rdy-drctl:
76 $ref: /schemas/types.yaml#/definitions/uin 69 $ref: /schemas/types.yaml#/definitions/uint32
77 description: | 70 description: |
78 Integer, representing the value of DRCTL 71 Integer, representing the value of DRCTL, the register controlling
79 the SPI_READY handling. Note that to ena 72 the SPI_READY handling. Note that to enable the DRCTL consideration,
80 the SPI_READY mode-flag needs to be set 73 the SPI_READY mode-flag needs to be set too.
81 Valid values are: 0 (disabled), 1 (edge- 74 Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).
82 enum: [0, 1, 2] 75 enum: [0, 1, 2]
83 76
84 required: 77 required:
85 - compatible 78 - compatible
86 - reg 79 - reg
87 - interrupts 80 - interrupts
88 - clocks 81 - clocks
89 - clock-names 82 - clock-names
90 83
91 unevaluatedProperties: false 84 unevaluatedProperties: false
92 85
93 examples: 86 examples:
94 - | 87 - |
95 #include <dt-bindings/clock/imx5-clock.h> 88 #include <dt-bindings/clock/imx5-clock.h>
96 89
97 spi@70010000 { 90 spi@70010000 {
98 #address-cells = <1>; 91 #address-cells = <1>;
99 #size-cells = <0>; 92 #size-cells = <0>;
100 compatible = "fsl,imx51-ecspi"; 93 compatible = "fsl,imx51-ecspi";
101 reg = <0x70010000 0x4000>; 94 reg = <0x70010000 0x4000>;
102 interrupts = <36>; 95 interrupts = <36>;
103 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GA 96 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
104 <&clks IMX5_CLK_ECSPI1_PER_GA 97 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
105 clock-names = "ipg", "per"; 98 clock-names = "ipg", "per";
106 }; 99 };
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