1 * Nuvoton FLASH Interface Unit (FIU) SPI Contr 1 * Nuvoton FLASH Interface Unit (FIU) SPI Controller
2 2
3 NPCM FIU supports single, dual and quad commun 3 NPCM FIU supports single, dual and quad communication interface.
4 4
5 The NPCM7XX supports three FIU modules, 5 The NPCM7XX supports three FIU modules,
6 FIU0 and FIUx supports two chip selects, 6 FIU0 and FIUx supports two chip selects,
7 FIU3 support four chip select. 7 FIU3 support four chip select.
8 8
9 The NPCM8XX supports four FIU modules, <<
10 FIU0 and FIUx supports two chip selects, <<
11 FIU1 and FIU3 supports four chip selects. <<
12 <<
13 Required properties: 9 Required properties:
14 - compatible : "nuvoton,npcm750-fiu" for Pol !! 10 - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
15 "nuvoton,npcm845- <<
16 - #address-cells : should be 1. 11 - #address-cells : should be 1.
17 - #size-cells : should be 0. 12 - #size-cells : should be 0.
18 - reg : the first contains the register loca 13 - reg : the first contains the register location and length,
19 the second contains the memory mappi 14 the second contains the memory mapping address and length
20 - reg-names: Should contain the reg names "c 15 - reg-names: Should contain the reg names "control" and "memory"
21 - clocks : phandle of FIU reference clock. 16 - clocks : phandle of FIU reference clock.
22 17
23 Required properties in case the pins can be mu 18 Required properties in case the pins can be muxed:
24 - pinctrl-names : a pinctrl state named "def 19 - pinctrl-names : a pinctrl state named "default" must be defined.
25 - pinctrl-0 : phandle referencing pin config 20 - pinctrl-0 : phandle referencing pin configuration of the device.
26 21
27 Optional property: 22 Optional property:
28 - nuvoton,spix-mode: enable spix-mode for an 23 - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
29 24
30 Aliases: 25 Aliases:
31 - All the FIU controller nodes should be repre 26 - All the FIU controller nodes should be represented in the aliases node using
32 the following format 'fiu{n}' where n is a u 27 the following format 'fiu{n}' where n is a unique number for the alias.
33 In the NPCM7XX BMC: 28 In the NPCM7XX BMC:
34 fiu0 represent fiu 0 controlle 29 fiu0 represent fiu 0 controller
35 fiu1 represent fiu 3 controlle 30 fiu1 represent fiu 3 controller
36 fiu2 represent fiu x controlle 31 fiu2 represent fiu x controller
37 32
38 In the NPCM8XX BMC: <<
39 fiu0 represent fiu 0 controlle <<
40 fiu1 represent fiu 1 controlle <<
41 fiu2 represent fiu 3 controlle <<
42 fiu3 represent fiu x controlle <<
43 <<
44 Example: 33 Example:
45 fiu3: spi@c00000000 { 34 fiu3: spi@c00000000 {
46 compatible = "nuvoton,npcm750-fiu"; 35 compatible = "nuvoton,npcm750-fiu";
47 #address-cells = <1>; 36 #address-cells = <1>;
48 #size-cells = <0>; 37 #size-cells = <0>;
49 reg = <0xfb000000 0x1000>, <0x80000000 38 reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
50 reg-names = "control", "memory"; 39 reg-names = "control", "memory";
51 clocks = <&clk NPCM7XX_CLK_AHB>; 40 clocks = <&clk NPCM7XX_CLK_AHB>;
52 pinctrl-names = "default"; 41 pinctrl-names = "default";
53 pinctrl-0 = <&spi3_pins>; 42 pinctrl-0 = <&spi3_pins>;
54 flash@0 { !! 43 spi-nor@0 {
55 ... 44 ...
56 }; 45 };
57 }; 46 };
58 47
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