1 Nuvoton NPCM Peripheral Serial Peripheral Inte 1 Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver
2 2
3 Nuvoton NPCM7xx SOC support two PSPI channels. 3 Nuvoton NPCM7xx SOC support two PSPI channels.
4 4
5 Required properties: 5 Required properties:
6 - compatible : "nuvoton,npcm750-pspi" for Pol 6 - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX.
7 "nuvoton,npcm8 7 "nuvoton,npcm845-pspi" for Arbel NPCM8XX.
8 - #address-cells : should be 1. see spi-bus.t 8 - #address-cells : should be 1. see spi-bus.txt
9 - #size-cells : should be 0. see spi-bus.txt 9 - #size-cells : should be 0. see spi-bus.txt
10 - specifies physical base address and size of 10 - specifies physical base address and size of the register.
11 - interrupts : contain PSPI interrupt. 11 - interrupts : contain PSPI interrupt.
12 - clocks : phandle of PSPI reference clock. 12 - clocks : phandle of PSPI reference clock.
13 - clock-names: Should be "clk_apb5". 13 - clock-names: Should be "clk_apb5".
14 - pinctrl-names : a pinctrl state named "defa 14 - pinctrl-names : a pinctrl state named "default" must be defined.
15 - pinctrl-0 : phandle referencing pin configu 15 - pinctrl-0 : phandle referencing pin configuration of the device.
16 - resets : phandle to the reset control for t 16 - resets : phandle to the reset control for this device.
17 - cs-gpios: Specifies the gpio pins to be use 17 - cs-gpios: Specifies the gpio pins to be used for chipselects.
18 See: Documentation/devicetree/bind 18 See: Documentation/devicetree/bindings/spi/spi-bus.txt
19 19
20 Optional properties: 20 Optional properties:
21 - clock-frequency : Input clock frequency to t 21 - clock-frequency : Input clock frequency to the PSPI block in Hz.
22 Default is 25000000 Hz. 22 Default is 25000000 Hz.
23 23
24 spi0: spi@f0200000 { 24 spi0: spi@f0200000 {
25 compatible = "nuvoton,npcm750-pspi"; 25 compatible = "nuvoton,npcm750-pspi";
26 reg = <0xf0200000 0x1000>; 26 reg = <0xf0200000 0x1000>;
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&pspi1_pins>; 28 pinctrl-0 = <&pspi1_pins>;
29 #address-cells = <1>; 29 #address-cells = <1>;
30 #size-cells = <0>; 30 #size-cells = <0>;
31 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVE 31 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&clk NPCM7XX_CLK_APB5>; 32 clocks = <&clk NPCM7XX_CLK_APB5>;
33 clock-names = "clk_apb5"; 33 clock-names = "clk_apb5";
34 resets = <&rstc NPCM7XX_RESET_IPSRST2 34 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>
35 cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW> 35 cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
36 }; 36 };
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