1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia, 4 $id: http://devicetree.org/schemas/spi/nvidia,tegra114-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NVIDIA Tegra114 SPI controller 7 title: NVIDIA Tegra114 SPI controller
8 8
9 maintainers: 9 maintainers:
10 - Thierry Reding <thierry.reding@gmail.com> 10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com> 11 - Jon Hunter <jonathanh@nvidia.com>
12 12
13 properties: 13 properties:
14 compatible: 14 compatible:
15 oneOf: 15 oneOf:
16 - const: nvidia,tegra114-spi 16 - const: nvidia,tegra114-spi
17 - items: 17 - items:
18 - enum: 18 - enum:
19 - nvidia,tegra210-spi 19 - nvidia,tegra210-spi
20 - nvidia,tegra124-spi 20 - nvidia,tegra124-spi
21 - const: nvidia,tegra114-spi 21 - const: nvidia,tegra114-spi
22 22
23 reg: 23 reg:
24 maxItems: 1 24 maxItems: 1
25 25
26 interrupts: 26 interrupts:
27 maxItems: 1 27 maxItems: 1
28 28
29 clocks: 29 clocks:
30 items: 30 items:
31 - description: SPI module clock 31 - description: SPI module clock
32 32
33 clock-names: 33 clock-names:
34 items: 34 items:
35 - const: spi 35 - const: spi
36 36
37 resets: 37 resets:
38 items: 38 items:
39 - description: SPI module reset 39 - description: SPI module reset
40 40
41 reset-names: 41 reset-names:
42 items: 42 items:
43 - const: spi 43 - const: spi
44 44
45 dmas: 45 dmas:
46 items: 46 items:
47 - description: DMA channel for the recep 47 - description: DMA channel for the reception FIFO
48 - description: DMA channel for the trans 48 - description: DMA channel for the transmission FIFO
49 49
50 dma-names: 50 dma-names:
51 items: 51 items:
52 - const: rx 52 - const: rx
53 - const: tx 53 - const: tx
54 54
55 spi-max-frequency: 55 spi-max-frequency:
56 description: Maximum SPI clocking speed of 56 description: Maximum SPI clocking speed of the controller in Hz.
57 $ref: /schemas/types.yaml#/definitions/uin 57 $ref: /schemas/types.yaml#/definitions/uint32
58 58
59 allOf: 59 allOf:
60 - $ref: spi-controller.yaml 60 - $ref: spi-controller.yaml
61 61
62 unevaluatedProperties: false 62 unevaluatedProperties: false
63 63
64 required: 64 required:
65 - compatible 65 - compatible
66 - reg 66 - reg
67 - interrupts 67 - interrupts
68 - clocks 68 - clocks
69 - clock-names 69 - clock-names
70 - resets 70 - resets
71 - reset-names 71 - reset-names
72 - dmas 72 - dmas
73 - dma-names 73 - dma-names
74 74
75 examples: 75 examples:
76 - | 76 - |
77 spi@7000d600 { 77 spi@7000d600 {
78 compatible = "nvidia,tegra114-spi"; 78 compatible = "nvidia,tegra114-spi";
79 reg = <0x7000d600 0x200>; 79 reg = <0x7000d600 0x200>;
80 interrupts = <0 82 0x04>; 80 interrupts = <0 82 0x04>;
81 clocks = <&tegra_car 44>; 81 clocks = <&tegra_car 44>;
82 clock-names = "spi"; 82 clock-names = "spi";
83 resets = <&tegra_car 44>; 83 resets = <&tegra_car 44>;
84 reset-names = "spi"; 84 reset-names = "spi";
85 dmas = <&apbdma 16>, <&apbdma 16>; 85 dmas = <&apbdma 16>, <&apbdma 16>;
86 dma-names = "rx", "tx"; 86 dma-names = "rx", "tx";
87 87
88 spi-max-frequency = <25000000>; 88 spi-max-frequency = <25000000>;
89 89
90 #address-cells = <1>; 90 #address-cells = <1>;
91 #size-cells = <0>; 91 #size-cells = <0>;
92 92
93 flash@0 { 93 flash@0 {
94 compatible = "jedec,spi-nor"; 94 compatible = "jedec,spi-nor";
95 reg = <0>; 95 reg = <0>;
96 spi-max-frequency = <20000000>; 96 spi-max-frequency = <20000000>;
97 nvidia,rx-clk-tap-delay = <0>; 97 nvidia,rx-clk-tap-delay = <0>;
98 nvidia,tx-clk-tap-delay = <16>; 98 nvidia,tx-clk-tap-delay = <16>;
99 }; 99 };
100 }; 100 };
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