1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: NVIDIA Tegra20 SFLASH controller
8
9 maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13 properties:
14 compatible:
15 const: nvidia,tegra20-sflash
16
17 reg:
18 maxItems: 1
19
20 interrupts:
21 maxItems: 1
22
23 clocks:
24 items:
25 - description: module clock
26
27 resets:
28 items:
29 - description: module reset
30
31 reset-names:
32 items:
33 - const: spi
34
35 dmas:
36 items:
37 - description: DMA channel used for rece
38 - description: DMA channel used for tran
39
40 dma-names:
41 items:
42 - const: rx
43 - const: tx
44
45 spi-max-frequency:
46 description: Maximum SPI clocking speed of
47 $ref: /schemas/types.yaml#/definitions/uin
48
49 allOf:
50 - $ref: spi-controller.yaml
51
52 unevaluatedProperties: false
53
54 required:
55 - compatible
56 - reg
57 - interrupts
58 - clocks
59 - resets
60 - reset-names
61 - dmas
62 - dma-names
63
64 examples:
65 - |
66 #include <dt-bindings/clock/tegra20-car.h>
67 #include <dt-bindings/interrupt-controller
68
69 spi@7000c380 {
70 compatible = "nvidia,tegra20-sflash";
71 reg = <0x7000c380 0x80>;
72 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVE
73 spi-max-frequency = <25000000>;
74 #address-cells = <1>;
75 #size-cells = <0>;
76 clocks = <&tegra_car TEGRA20_CLK_SPI>;
77 resets = <&tegra_car 43>;
78 reset-names = "spi";
79 dmas = <&apbdma 11>, <&apbdma 11>;
80 dma-names = "rx", "tx";
81 };
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