1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> 2
2 %YAML 1.2 3 %YAML 1.2
3 --- 4 ---
4 $id: http://devicetree.org/schemas/spi/qcom,sp !! 5 $id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
5 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
6 7
7 title: Qualcomm Quad Serial Peripheral Interfa 8 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
8 9
9 maintainers: 10 maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org !! 11 - Mukesh Savaliya <msavaliy@codeaurora.org>
>> 12 - Akash Asthana <akashast@codeaurora.org>
11 13
12 description: The QSPI controller allows SPI pr 14 description: The QSPI controller allows SPI protocol communication in single,
13 dual, or quad wire transmission modes for re 15 dual, or quad wire transmission modes for read/write access to slaves such
14 as NOR flash. 16 as NOR flash.
15 17
16 allOf: 18 allOf:
17 - $ref: /schemas/spi/spi-controller.yaml# 19 - $ref: /schemas/spi/spi-controller.yaml#
18 20
19 properties: 21 properties:
20 compatible: 22 compatible:
21 items: 23 items:
22 - enum: 24 - enum:
23 - qcom,sc7180-qspi 25 - qcom,sc7180-qspi
24 - qcom,sc7280-qspi 26 - qcom,sc7280-qspi
25 - qcom,sdm845-qspi 27 - qcom,sdm845-qspi
26 28
27 - const: qcom,qspi-v1 29 - const: qcom,qspi-v1
28 30
29 reg: 31 reg:
30 maxItems: 1 32 maxItems: 1
31 33
32 iommus: <<
33 maxItems: 1 <<
34 <<
35 interrupts: 34 interrupts:
36 maxItems: 1 35 maxItems: 1
37 36
38 clock-names: 37 clock-names:
39 items: 38 items:
40 - const: iface 39 - const: iface
41 - const: core 40 - const: core
42 41
43 clocks: 42 clocks:
44 items: 43 items:
45 - description: AHB clock 44 - description: AHB clock
46 - description: QSPI core clock 45 - description: QSPI core clock
47 46
48 interconnects: 47 interconnects:
49 minItems: 1 48 minItems: 1
50 maxItems: 2 49 maxItems: 2
51 50
52 interconnect-names: 51 interconnect-names:
53 minItems: 1 52 minItems: 1
54 items: 53 items:
55 - const: qspi-config 54 - const: qspi-config
56 - const: qspi-memory 55 - const: qspi-memory
57 56
58 operating-points-v2: true <<
59 <<
60 power-domains: <<
61 maxItems: 1 <<
62 <<
63 required: 57 required:
64 - compatible 58 - compatible
65 - reg 59 - reg
66 - interrupts 60 - interrupts
67 - clock-names 61 - clock-names
68 - clocks 62 - clocks
69 63
70 unevaluatedProperties: false 64 unevaluatedProperties: false
71 65
72 examples: 66 examples:
73 - | 67 - |
74 #include <dt-bindings/clock/qcom,gcc-sdm84 68 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
75 #include <dt-bindings/interrupt-controller 69 #include <dt-bindings/interrupt-controller/arm-gic.h>
76 70
77 soc: soc { 71 soc: soc {
78 #address-cells = <2>; 72 #address-cells = <2>;
79 #size-cells = <2>; 73 #size-cells = <2>;
80 74
81 qspi: spi@88df000 { 75 qspi: spi@88df000 {
82 compatible = "qcom,sdm845-qspi", " 76 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
83 reg = <0 0x88df000 0 0x600>; 77 reg = <0 0x88df000 0 0x600>;
84 #address-cells = <1>; 78 #address-cells = <1>;
85 #size-cells = <0>; 79 #size-cells = <0>;
86 interrupts = <GIC_SPI 82 IRQ_TYPE_ 80 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
87 clock-names = "iface", "core"; 81 clock-names = "iface", "core";
88 clocks = <&gcc GCC_QSPI_CNOC_PERIP 82 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
89 <&gcc GCC_QSPI_CORE_C 83 <&gcc GCC_QSPI_CORE_CLK>;
90 84
91 flash@0 { 85 flash@0 {
92 compatible = "jedec,spi-nor"; 86 compatible = "jedec,spi-nor";
93 reg = <0>; 87 reg = <0>;
94 spi-max-frequency = <25000000> 88 spi-max-frequency = <25000000>;
95 spi-tx-bus-width = <2>; 89 spi-tx-bus-width = <2>;
96 spi-rx-bus-width = <2>; 90 spi-rx-bus-width = <2>;
97 }; 91 };
>> 92
98 }; 93 };
99 }; 94 };
100 ... 95 ...
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