1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> 2
2 %YAML 1.2 3 %YAML 1.2
3 --- 4 ---
4 $id: http://devicetree.org/schemas/spi/qcom,sp !! 5 $id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
5 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
6 7
7 title: Qualcomm Quad Serial Peripheral Interfa 8 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
8 9
9 maintainers: 10 maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org !! 11 - Mukesh Savaliya <msavaliy@codeaurora.org>
>> 12 - Akash Asthana <akashast@codeaurora.org>
11 13
12 description: The QSPI controller allows SPI pr !! 14 description:
13 dual, or quad wire transmission modes for re !! 15 The QSPI controller allows SPI protocol communication in single, dual, or quad
14 as NOR flash. !! 16 wire transmission modes for read/write access to slaves such as NOR flash.
15 17
16 allOf: 18 allOf:
17 - $ref: /schemas/spi/spi-controller.yaml# !! 19 - $ref: /spi/spi-controller.yaml#
18 20
19 properties: 21 properties:
20 compatible: 22 compatible:
21 items: 23 items:
22 - enum: !! 24 - const: qcom,sdm845-qspi
23 - qcom,sc7180-qspi <<
24 - qcom,sc7280-qspi <<
25 - qcom,sdm845-qspi <<
26 <<
27 - const: qcom,qspi-v1 25 - const: qcom,qspi-v1
28 26
29 reg: 27 reg:
30 maxItems: 1 28 maxItems: 1
31 29
32 iommus: <<
33 maxItems: 1 <<
34 <<
35 interrupts: 30 interrupts:
36 maxItems: 1 31 maxItems: 1
37 32
38 clock-names: 33 clock-names:
39 items: 34 items:
40 - const: iface 35 - const: iface
41 - const: core 36 - const: core
42 37
43 clocks: 38 clocks:
44 items: 39 items:
45 - description: AHB clock 40 - description: AHB clock
46 - description: QSPI core clock 41 - description: QSPI core clock
47 42
48 interconnects: 43 interconnects:
49 minItems: 1 44 minItems: 1
50 maxItems: 2 45 maxItems: 2
51 46
52 interconnect-names: 47 interconnect-names:
53 minItems: 1 <<
54 items: 48 items:
55 - const: qspi-config 49 - const: qspi-config
56 - const: qspi-memory 50 - const: qspi-memory
57 51
58 operating-points-v2: true <<
59 <<
60 power-domains: <<
61 maxItems: 1 <<
62 <<
63 required: 52 required:
64 - compatible 53 - compatible
65 - reg 54 - reg
66 - interrupts 55 - interrupts
67 - clock-names 56 - clock-names
68 - clocks 57 - clocks
69 58
70 unevaluatedProperties: false <<
71 <<
72 examples: 59 examples:
73 - | 60 - |
74 #include <dt-bindings/clock/qcom,gcc-sdm84 61 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
75 #include <dt-bindings/interrupt-controller 62 #include <dt-bindings/interrupt-controller/arm-gic.h>
76 63
77 soc: soc { 64 soc: soc {
78 #address-cells = <2>; 65 #address-cells = <2>;
79 #size-cells = <2>; 66 #size-cells = <2>;
80 67
81 qspi: spi@88df000 { 68 qspi: spi@88df000 {
82 compatible = "qcom,sdm845-qspi", " 69 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
83 reg = <0 0x88df000 0 0x600>; 70 reg = <0 0x88df000 0 0x600>;
84 #address-cells = <1>; 71 #address-cells = <1>;
85 #size-cells = <0>; 72 #size-cells = <0>;
86 interrupts = <GIC_SPI 82 IRQ_TYPE_ 73 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
87 clock-names = "iface", "core"; 74 clock-names = "iface", "core";
88 clocks = <&gcc GCC_QSPI_CNOC_PERIP 75 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
89 <&gcc GCC_QSPI_CORE_C 76 <&gcc GCC_QSPI_CORE_CLK>;
90 77
91 flash@0 { 78 flash@0 {
92 compatible = "jedec,spi-nor"; 79 compatible = "jedec,spi-nor";
93 reg = <0>; 80 reg = <0>;
94 spi-max-frequency = <25000000> 81 spi-max-frequency = <25000000>;
95 spi-tx-bus-width = <2>; 82 spi-tx-bus-width = <2>;
96 spi-rx-bus-width = <2>; 83 spi-rx-bus-width = <2>;
97 }; 84 };
>> 85
98 }; 86 };
99 }; 87 };
100 ... 88 ...
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