1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> 2 2 %YAML 1.2 3 %YAML 1.2 3 --- 4 --- 4 $id: http://devicetree.org/schemas/spi/qcom,sp !! 5 $id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" 5 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7 7 title: Qualcomm Quad Serial Peripheral Interfa 8 title: Qualcomm Quad Serial Peripheral Interface (QSPI) 8 9 9 maintainers: 10 maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org 11 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12 12 description: The QSPI controller allows SPI pr 13 description: The QSPI controller allows SPI protocol communication in single, 13 dual, or quad wire transmission modes for re 14 dual, or quad wire transmission modes for read/write access to slaves such 14 as NOR flash. 15 as NOR flash. 15 16 16 allOf: 17 allOf: 17 - $ref: /schemas/spi/spi-controller.yaml# 18 - $ref: /schemas/spi/spi-controller.yaml# 18 19 19 properties: 20 properties: 20 compatible: 21 compatible: 21 items: 22 items: 22 - enum: 23 - enum: 23 - qcom,sc7180-qspi 24 - qcom,sc7180-qspi 24 - qcom,sc7280-qspi 25 - qcom,sc7280-qspi 25 - qcom,sdm845-qspi 26 - qcom,sdm845-qspi 26 27 27 - const: qcom,qspi-v1 28 - const: qcom,qspi-v1 28 29 29 reg: 30 reg: 30 maxItems: 1 31 maxItems: 1 31 32 32 iommus: << 33 maxItems: 1 << 34 << 35 interrupts: 33 interrupts: 36 maxItems: 1 34 maxItems: 1 37 35 38 clock-names: 36 clock-names: 39 items: 37 items: 40 - const: iface 38 - const: iface 41 - const: core 39 - const: core 42 40 43 clocks: 41 clocks: 44 items: 42 items: 45 - description: AHB clock 43 - description: AHB clock 46 - description: QSPI core clock 44 - description: QSPI core clock 47 45 48 interconnects: 46 interconnects: 49 minItems: 1 47 minItems: 1 50 maxItems: 2 48 maxItems: 2 51 49 52 interconnect-names: 50 interconnect-names: 53 minItems: 1 51 minItems: 1 54 items: 52 items: 55 - const: qspi-config 53 - const: qspi-config 56 - const: qspi-memory 54 - const: qspi-memory 57 55 58 operating-points-v2: true << 59 << 60 power-domains: << 61 maxItems: 1 << 62 << 63 required: 56 required: 64 - compatible 57 - compatible 65 - reg 58 - reg 66 - interrupts 59 - interrupts 67 - clock-names 60 - clock-names 68 - clocks 61 - clocks 69 62 70 unevaluatedProperties: false 63 unevaluatedProperties: false 71 64 72 examples: 65 examples: 73 - | 66 - | 74 #include <dt-bindings/clock/qcom,gcc-sdm84 67 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 75 #include <dt-bindings/interrupt-controller 68 #include <dt-bindings/interrupt-controller/arm-gic.h> 76 69 77 soc: soc { 70 soc: soc { 78 #address-cells = <2>; 71 #address-cells = <2>; 79 #size-cells = <2>; 72 #size-cells = <2>; 80 73 81 qspi: spi@88df000 { 74 qspi: spi@88df000 { 82 compatible = "qcom,sdm845-qspi", " 75 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 83 reg = <0 0x88df000 0 0x600>; 76 reg = <0 0x88df000 0 0x600>; 84 #address-cells = <1>; 77 #address-cells = <1>; 85 #size-cells = <0>; 78 #size-cells = <0>; 86 interrupts = <GIC_SPI 82 IRQ_TYPE_ 79 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 87 clock-names = "iface", "core"; 80 clock-names = "iface", "core"; 88 clocks = <&gcc GCC_QSPI_CNOC_PERIP 81 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 89 <&gcc GCC_QSPI_CORE_C 82 <&gcc GCC_QSPI_CORE_CLK>; 90 83 91 flash@0 { 84 flash@0 { 92 compatible = "jedec,spi-nor"; 85 compatible = "jedec,spi-nor"; 93 reg = <0>; 86 reg = <0>; 94 spi-max-frequency = <25000000> 87 spi-max-frequency = <25000000>; 95 spi-tx-bus-width = <2>; 88 spi-tx-bus-width = <2>; 96 spi-rx-bus-width = <2>; 89 spi-rx-bus-width = <2>; 97 }; 90 }; >> 91 98 }; 92 }; 99 }; 93 }; 100 ... 94 ...
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