1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 %YAML 1.2 2 %YAML 1.2 3 --- 3 --- 4 $id: http://devicetree.org/schemas/spi/qcom,sp 4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml# 5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 title: Qualcomm Quad Serial Peripheral Interfa 7 title: Qualcomm Quad Serial Peripheral Interface (QSPI) 8 8 9 maintainers: 9 maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 11 12 description: The QSPI controller allows SPI pr 12 description: The QSPI controller allows SPI protocol communication in single, 13 dual, or quad wire transmission modes for re 13 dual, or quad wire transmission modes for read/write access to slaves such 14 as NOR flash. 14 as NOR flash. 15 15 16 allOf: 16 allOf: 17 - $ref: /schemas/spi/spi-controller.yaml# 17 - $ref: /schemas/spi/spi-controller.yaml# 18 18 19 properties: 19 properties: 20 compatible: 20 compatible: 21 items: 21 items: 22 - enum: 22 - enum: 23 - qcom,sc7180-qspi 23 - qcom,sc7180-qspi 24 - qcom,sc7280-qspi 24 - qcom,sc7280-qspi 25 - qcom,sdm845-qspi 25 - qcom,sdm845-qspi 26 26 27 - const: qcom,qspi-v1 27 - const: qcom,qspi-v1 28 28 29 reg: 29 reg: 30 maxItems: 1 30 maxItems: 1 31 31 32 iommus: << 33 maxItems: 1 << 34 << 35 interrupts: 32 interrupts: 36 maxItems: 1 33 maxItems: 1 37 34 38 clock-names: 35 clock-names: 39 items: 36 items: 40 - const: iface 37 - const: iface 41 - const: core 38 - const: core 42 39 43 clocks: 40 clocks: 44 items: 41 items: 45 - description: AHB clock 42 - description: AHB clock 46 - description: QSPI core clock 43 - description: QSPI core clock 47 44 48 interconnects: 45 interconnects: 49 minItems: 1 46 minItems: 1 50 maxItems: 2 47 maxItems: 2 51 48 52 interconnect-names: 49 interconnect-names: 53 minItems: 1 50 minItems: 1 54 items: 51 items: 55 - const: qspi-config 52 - const: qspi-config 56 - const: qspi-memory 53 - const: qspi-memory 57 54 58 operating-points-v2: true 55 operating-points-v2: true 59 56 60 power-domains: 57 power-domains: 61 maxItems: 1 58 maxItems: 1 62 59 63 required: 60 required: 64 - compatible 61 - compatible 65 - reg 62 - reg 66 - interrupts 63 - interrupts 67 - clock-names 64 - clock-names 68 - clocks 65 - clocks 69 66 70 unevaluatedProperties: false 67 unevaluatedProperties: false 71 68 72 examples: 69 examples: 73 - | 70 - | 74 #include <dt-bindings/clock/qcom,gcc-sdm84 71 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 75 #include <dt-bindings/interrupt-controller 72 #include <dt-bindings/interrupt-controller/arm-gic.h> 76 73 77 soc: soc { 74 soc: soc { 78 #address-cells = <2>; 75 #address-cells = <2>; 79 #size-cells = <2>; 76 #size-cells = <2>; 80 77 81 qspi: spi@88df000 { 78 qspi: spi@88df000 { 82 compatible = "qcom,sdm845-qspi", " 79 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 83 reg = <0 0x88df000 0 0x600>; 80 reg = <0 0x88df000 0 0x600>; 84 #address-cells = <1>; 81 #address-cells = <1>; 85 #size-cells = <0>; 82 #size-cells = <0>; 86 interrupts = <GIC_SPI 82 IRQ_TYPE_ 83 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 87 clock-names = "iface", "core"; 84 clock-names = "iface", "core"; 88 clocks = <&gcc GCC_QSPI_CNOC_PERIP 85 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 89 <&gcc GCC_QSPI_CORE_C 86 <&gcc GCC_QSPI_CORE_CLK>; 90 87 91 flash@0 { 88 flash@0 { 92 compatible = "jedec,spi-nor"; 89 compatible = "jedec,spi-nor"; 93 reg = <0>; 90 reg = <0>; 94 spi-max-frequency = <25000000> 91 spi-max-frequency = <25000000>; 95 spi-tx-bus-width = <2>; 92 spi-tx-bus-width = <2>; 96 spi-rx-bus-width = <2>; 93 spi-rx-bus-width = <2>; 97 }; 94 }; 98 }; 95 }; 99 }; 96 }; 100 ... 97 ...
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